/*
 * Copyright (c) [2020], MediaTek Inc. All rights reserved.
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. and/or its licensors.
 * Except as otherwise provided in the applicable licensing terms with
 * MediaTek Inc. and/or its licensors, any reproduction, modification, use or
 * disclosure of MediaTek Software, and information contained herein, in whole
 * or in part, shall be strictly prohibited.
*/
//[File]            : bn0_wf_lpon_top.h
//[Revision time]   : Fri Aug 31 13:02:17 2018
//[Description]     : This file is auto generated by CODA
//[Copyright]       : Copyright (C) 2018 Mediatek Incorportion. All rights reserved.

#ifndef __BN0_WF_LPON_TOP_REGS_H__
#define __BN0_WF_LPON_TOP_REGS_H__

#include "hal_common.h"

#ifdef __cplusplus
extern "C" {
#endif


//****************************************************************************
//
//                     BN0_WF_LPON_TOP CR Definitions                     
//
//****************************************************************************

#define BN0_WF_LPON_TOP_BASE                                   0x820EB000

#define BN0_WF_LPON_TOP_TT0SBOR1_ADDR                          (BN0_WF_LPON_TOP_BASE + 0x000) // B000
#define BN0_WF_LPON_TOP_TT0SBOR2_ADDR                          (BN0_WF_LPON_TOP_BASE + 0x004) // B004
#define BN0_WF_LPON_TOP_TT0SBOR3_ADDR                          (BN0_WF_LPON_TOP_BASE + 0x008) // B008
#define BN0_WF_LPON_TOP_TT0SBOR4_ADDR                          (BN0_WF_LPON_TOP_BASE + 0x00c) // B00C
#define BN0_WF_LPON_TOP_TT0SBOR5_ADDR                          (BN0_WF_LPON_TOP_BASE + 0x010) // B010
#define BN0_WF_LPON_TOP_TT0SBOR6_ADDR                          (BN0_WF_LPON_TOP_BASE + 0x014) // B014
#define BN0_WF_LPON_TOP_TT0SBOR7_ADDR                          (BN0_WF_LPON_TOP_BASE + 0x018) // B018
#define BN0_WF_LPON_TOP_TT0SBOR8_ADDR                          (BN0_WF_LPON_TOP_BASE + 0x01c) // B01C
#define BN0_WF_LPON_TOP_TT0SBOR9_ADDR                          (BN0_WF_LPON_TOP_BASE + 0x020) // B020
#define BN0_WF_LPON_TOP_TT0SBOR10_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x024) // B024
#define BN0_WF_LPON_TOP_TT0SBOR11_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x028) // B028
#define BN0_WF_LPON_TOP_TT0SBOR12_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x02c) // B02C
#define BN0_WF_LPON_TOP_TT0SBOR13_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x030) // B030
#define BN0_WF_LPON_TOP_TT0SBOR14_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x034) // B034
#define BN0_WF_LPON_TOP_TT0SBOR15_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x038) // B038
#define BN0_WF_LPON_TOP_SBTOR1_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x03c) // B03C
#define BN0_WF_LPON_TOP_SBTOR2_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x040) // B040
#define BN0_WF_LPON_TOP_SBTOR3_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x044) // B044
#define BN0_WF_LPON_TOP_SBTOR4_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x048) // B048
#define BN0_WF_LPON_TOP_SBTOR5_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x04c) // B04C
#define BN0_WF_LPON_TOP_SBTOR6_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x050) // B050
#define BN0_WF_LPON_TOP_SBTOR7_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x054) // B054
#define BN0_WF_LPON_TOP_SBTOR8_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x058) // B058
#define BN0_WF_LPON_TOP_SBTOR9_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x05c) // B05C
#define BN0_WF_LPON_TOP_SBTOR10_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x060) // B060
#define BN0_WF_LPON_TOP_SBTOR11_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x064) // B064
#define BN0_WF_LPON_TOP_SBTOR12_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x068) // B068
#define BN0_WF_LPON_TOP_SBTOR13_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x06c) // B06C
#define BN0_WF_LPON_TOP_SBTOR14_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x070) // B070
#define BN0_WF_LPON_TOP_SBTOR15_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x074) // B074
#define BN0_WF_LPON_TOP_SBTOCR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x078) // B078
#define BN0_WF_LPON_TOP_TSELR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x07c) // B07C
#define BN0_WF_LPON_TOP_UTTR0_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x080) // B080
#define BN0_WF_LPON_TOP_UTTR1_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x084) // B084
#define BN0_WF_LPON_TOP_LTTR0_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x088) // B088
#define BN0_WF_LPON_TOP_LTTR1_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x08c) // B08C
#define BN0_WF_LPON_TOP_LTTR2_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x090) // B090
#define BN0_WF_LPON_TOP_LTTR3_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x094) // B094
#define BN0_WF_LPON_TOP_LTTR4_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x098) // B098
#define BN0_WF_LPON_TOP_LTTR5_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x09c) // B09C
#define BN0_WF_LPON_TOP_LTTR6_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x0a0) // B0A0
#define BN0_WF_LPON_TOP_LTTR7_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x0a4) // B0A4
#define BN0_WF_LPON_TOP_T0CR_ADDR                              (BN0_WF_LPON_TOP_BASE + 0x0a8) // B0A8
#define BN0_WF_LPON_TOP_T1CR_ADDR                              (BN0_WF_LPON_TOP_BASE + 0x0ac) // B0AC
#define BN0_WF_LPON_TOP_T2CR_ADDR                              (BN0_WF_LPON_TOP_BASE + 0x0b0) // B0B0
#define BN0_WF_LPON_TOP_T3CR_ADDR                              (BN0_WF_LPON_TOP_BASE + 0x0b4) // B0B4
#define BN0_WF_LPON_TOP_T0DVR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x0b8) // B0B8
#define BN0_WF_LPON_TOP_T1DVR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x0bc) // B0BC
#define BN0_WF_LPON_TOP_T2DVR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x0c0) // B0C0
#define BN0_WF_LPON_TOP_T3DVR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x0c4) // B0C4
#define BN0_WF_LPON_TOP_T0STR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x0c8) // B0C8
#define BN0_WF_LPON_TOP_T1STR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x0cc) // B0CC
#define BN0_WF_LPON_TOP_T2STR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x0d0) // B0D0
#define BN0_WF_LPON_TOP_T3STR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x0d4) // B0D4
#define BN0_WF_LPON_TOP_T0TPCR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x0d8) // B0D8
#define BN0_WF_LPON_TOP_T1TPCR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x0dc) // B0DC
#define BN0_WF_LPON_TOP_T2TPCR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x0e0) // B0E0
#define BN0_WF_LPON_TOP_T3TPCR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x0e4) // B0E4
#define BN0_WF_LPON_TOP_TT0STR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x0e8) // B0E8
#define BN0_WF_LPON_TOP_TT1STR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x0ec) // B0EC
#define BN0_WF_LPON_TOP_TT2STR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x0f0) // B0F0
#define BN0_WF_LPON_TOP_TT3STR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x0f4) // B0F4
#define BN0_WF_LPON_TOP_TT0TPCR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x0f8) // B0F8
#define BN0_WF_LPON_TOP_TT1TPCR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x0fc) // B0FC
#define BN0_WF_LPON_TOP_TT2TPCR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x100) // B100
#define BN0_WF_LPON_TOP_TT3TPCR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x104) // B104
#define BN0_WF_LPON_TOP_TT4TPCR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x108) // B108
#define BN0_WF_LPON_TOP_TT5TPCR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x10c) // B10C
#define BN0_WF_LPON_TOP_TT6TPCR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x110) // B110
#define BN0_WF_LPON_TOP_TT7TPCR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x114) // B114
#define BN0_WF_LPON_TOP_T0SFR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x118) // B118
#define BN0_WF_LPON_TOP_T1SFR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x11c) // B11C
#define BN0_WF_LPON_TOP_T2SFR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x120) // B120
#define BN0_WF_LPON_TOP_T3SFR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x124) // B124
#define BN0_WF_LPON_TOP_TT0SFR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x128) // B128
#define BN0_WF_LPON_TOP_TT1SFR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x12c) // B12C
#define BN0_WF_LPON_TOP_TT2SFR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x130) // B130
#define BN0_WF_LPON_TOP_TT3SFR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x134) // B134
#define BN0_WF_LPON_TOP_TTR_ADDR                               (BN0_WF_LPON_TOP_BASE + 0x138) // B138
#define BN0_WF_LPON_TOP_TTR1_ADDR                              (BN0_WF_LPON_TOP_BASE + 0x13c) // B13C
#define BN0_WF_LPON_TOP_TTR2_ADDR                              (BN0_WF_LPON_TOP_BASE + 0x140) // B140
#define BN0_WF_LPON_TOP_TTR3_ADDR                              (BN0_WF_LPON_TOP_BASE + 0x144) // B144
#define BN0_WF_LPON_TOP_TTSR_ADDR                              (BN0_WF_LPON_TOP_BASE + 0x148) // B148
#define BN0_WF_LPON_TOP_TTSR1_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x14c) // B14C
#define BN0_WF_LPON_TOP_TTSR2_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x150) // B150
#define BN0_WF_LPON_TOP_TTSR3_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x154) // B154
#define BN0_WF_LPON_TOP_TTTR0_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x158) // B158
#define BN0_WF_LPON_TOP_TTTR1_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x15c) // B15C
#define BN0_WF_LPON_TOP_TTTR2_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x160) // B160
#define BN0_WF_LPON_TOP_TTTR3_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x164) // B164
#define BN0_WF_LPON_TOP_TFRSR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x168) // B168
#define BN0_WF_LPON_TOP_TGTR_ADDR                              (BN0_WF_LPON_TOP_BASE + 0x16c) // B16C
#define BN0_WF_LPON_TOP_TICKER0_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x170) // B170
#define BN0_WF_LPON_TOP_TICKER1_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x174) // B174
#define BN0_WF_LPON_TOP_TICKER2_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x178) // B178
#define BN0_WF_LPON_TOP_TICKER3_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x17c) // B17C
#define BN0_WF_LPON_TOP_TICKER4_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x180) // B180
#define BN0_WF_LPON_TOP_TICKER5_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x184) // B184
#define BN0_WF_LPON_TOP_TICKER6_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x188) // B188
#define BN0_WF_LPON_TOP_TICKER7_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x18c) // B18C
#define BN0_WF_LPON_TOP_TICKER8_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x190) // B190
#define BN0_WF_LPON_TOP_TICKER9_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x194) // B194
#define BN0_WF_LPON_TOP_PISR_ADDR                              (BN0_WF_LPON_TOP_BASE + 0x198) // B198
#define BN0_WF_LPON_TOP_PTTISR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x19c) // B19C
#define BN0_WF_LPON_TOP_BTEIR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x1a0) // B1A0
#define BN0_WF_LPON_TOP_TIMTR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x1a4) // B1A4
#define BN0_WF_LPON_TOP_SPCR_ADDR                              (BN0_WF_LPON_TOP_BASE + 0x1a8) // B1A8
#define BN0_WF_LPON_TOP_SPCR1_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x1ac) // B1AC
#define BN0_WF_LPON_TOP_BCNTR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x1b0) // B1B0
#define BN0_WF_LPON_TOP_TCLCR_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x1b4) // B1B4
#define BN0_WF_LPON_TOP_BACKWARD_ADDR                          (BN0_WF_LPON_TOP_BASE + 0x1b8) // B1B8
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_ADDR                       (BN0_WF_LPON_TOP_BASE + 0x1bc) // B1BC
#define BN0_WF_LPON_TOP_LGRX_BCNCR1_ADDR                       (BN0_WF_LPON_TOP_BASE + 0x1c0) // B1C0
#define BN0_WF_LPON_TOP_LGRX_BCNCR2_ADDR                       (BN0_WF_LPON_TOP_BASE + 0x1c4) // B1C4
#define BN0_WF_LPON_TOP_WLANCKCALCR0_ADDR                      (BN0_WF_LPON_TOP_BASE + 0x1c8) // B1C8
#define BN0_WF_LPON_TOP_WLANCKCALCR1_ADDR                      (BN0_WF_LPON_TOP_BASE + 0x1cc) // B1CC
#define BN0_WF_LPON_TOP_TIMSPCR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x1d0) // B1D0
#define BN0_WF_LPON_TOP_CTBCNCR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x1d4) // B1D4
#define BN0_WF_LPON_TOP_LBCNTOR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x1d8) // B1D8
#define BN0_WF_LPON_TOP_LTIMTOR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x1dc) // B1DC
#define BN0_WF_LPON_TOP_LBMCTOR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x1e0) // B1E0
#define BN0_WF_LPON_TOP_LTMBCTOR_ADDR                          (BN0_WF_LPON_TOP_BASE + 0x1e4) // B1E4
#define BN0_WF_LPON_TOP_LLGRBRR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x1e8) // B1E8
#define BN0_WF_LPON_TOP_LLGRBLR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x1ec) // B1EC
#define BN0_WF_LPON_TOP_LDTIMCR_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x1f0) // B1F0
#define BN0_WF_LPON_TOP_LMTBDTCR_ADDR                          (BN0_WF_LPON_TOP_BASE + 0x1f4) // B1F4
#define BN0_WF_LPON_TOP_BUSY_SEL_ADDR                          (BN0_WF_LPON_TOP_BASE + 0x1f8) // B1F8
#define BN0_WF_LPON_TOP_LFBCR0_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x1fc) // B1FC
#define BN0_WF_LPON_TOP_PBCR0_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x200) // B200
#define BN0_WF_LPON_TOP_NANCR0_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x204) // B204
#define BN0_WF_LPON_TOP_NANCR1_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x208) // B208
#define BN0_WF_LPON_TOP_NANCR2_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x20c) // B20C
#define BN0_WF_LPON_TOP_AUDIO0_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x210) // B210
#define BN0_WF_LPON_TOP_AUDIO1_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x214) // B214
#define BN0_WF_LPON_TOP_AUDIO2_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x218) // B218
#define BN0_WF_LPON_TOP_TRAPUMAC_ADDR                          (BN0_WF_LPON_TOP_BASE + 0x21c) // B21C
#define BN0_WF_LPON_TOP_TRAPUMAC_DIS_ADDR                      (BN0_WF_LPON_TOP_BASE + 0x220) // B220
#define BN0_WF_LPON_TOP_NEXT_TRAPUMAC_ADDR                     (BN0_WF_LPON_TOP_BASE + 0x224) // B224
#define BN0_WF_LPON_TOP_CGFIX_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x228) // B228
#define BN0_WF_LPON_TOP_PHYOUTCR_ADDR                          (BN0_WF_LPON_TOP_BASE + 0x22c) // B22C
#define BN0_WF_LPON_TOP_TWT0CR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x230) // B230
#define BN0_WF_LPON_TOP_TWT1CR_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x234) // B234
#define BN0_WF_LPON_TOP_TWT0VR0_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x238) // B238
#define BN0_WF_LPON_TOP_TWT0VR1_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x23c) // B23C
#define BN0_WF_LPON_TOP_TWT1VR0_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x240) // B240
#define BN0_WF_LPON_TOP_TWT1VR1_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x244) // B244
#define BN0_WF_LPON_TOP_TWT0TR0_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x248) // B248
#define BN0_WF_LPON_TOP_TWT0TR1_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x24c) // B24C
#define BN0_WF_LPON_TOP_TWT1TR0_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x250) // B250
#define BN0_WF_LPON_TOP_TWT1TR1_ADDR                           (BN0_WF_LPON_TOP_BASE + 0x254) // B254
#define BN0_WF_LPON_TOP_MUEDCA0CR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x258) // B258
#define BN0_WF_LPON_TOP_MUEDCA1CR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x25c) // B25C
#define BN0_WF_LPON_TOP_MUEDCA2CR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x260) // B260
#define BN0_WF_LPON_TOP_MUEDCA3CR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x264) // B264
#define BN0_WF_LPON_TOP_MUEDCA4CR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x268) // B268
#define BN0_WF_LPON_TOP_MUEDCA5CR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x26c) // B26C
#define BN0_WF_LPON_TOP_MUEDCA6CR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x270) // B270
#define BN0_WF_LPON_TOP_MUEDCA7CR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x274) // B274
#define BN0_WF_LPON_TOP_MUEDCA8CR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x278) // B278
#define BN0_WF_LPON_TOP_MUEDCA9CR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x27c) // B27C
#define BN0_WF_LPON_TOP_MUEDCA10CR_ADDR                        (BN0_WF_LPON_TOP_BASE + 0x280) // B280
#define BN0_WF_LPON_TOP_MUEDCA11CR_ADDR                        (BN0_WF_LPON_TOP_BASE + 0x284) // B284
#define BN0_WF_LPON_TOP_MUEDCA12CR_ADDR                        (BN0_WF_LPON_TOP_BASE + 0x288) // B288
#define BN0_WF_LPON_TOP_MUEDCA13CR_ADDR                        (BN0_WF_LPON_TOP_BASE + 0x28c) // B28C
#define BN0_WF_LPON_TOP_MUEDCA14CR_ADDR                        (BN0_WF_LPON_TOP_BASE + 0x290) // B290
#define BN0_WF_LPON_TOP_MUEDCA15CR_ADDR                        (BN0_WF_LPON_TOP_BASE + 0x294) // B294
#define BN0_WF_LPON_TOP_MUEDCA0TR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x298) // B298
#define BN0_WF_LPON_TOP_MUEDCA1TR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x29c) // B29C
#define BN0_WF_LPON_TOP_MUEDCA2TR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x2a0) // B2A0
#define BN0_WF_LPON_TOP_MUEDCA3TR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x2a4) // B2A4
#define BN0_WF_LPON_TOP_MUEDCA4TR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x2a8) // B2A8
#define BN0_WF_LPON_TOP_MUEDCA5TR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x2ac) // B2AC
#define BN0_WF_LPON_TOP_MUEDCA6TR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x2b0) // B2B0
#define BN0_WF_LPON_TOP_MUEDCA7TR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x2b4) // B2B4
#define BN0_WF_LPON_TOP_MUEDCA8TR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x2b8) // B2B8
#define BN0_WF_LPON_TOP_MUEDCA9TR_ADDR                         (BN0_WF_LPON_TOP_BASE + 0x2bc) // B2BC
#define BN0_WF_LPON_TOP_MUEDCA10TR_ADDR                        (BN0_WF_LPON_TOP_BASE + 0x2c0) // B2C0
#define BN0_WF_LPON_TOP_MUEDCA11TR_ADDR                        (BN0_WF_LPON_TOP_BASE + 0x2c4) // B2C4
#define BN0_WF_LPON_TOP_MUEDCA12TR_ADDR                        (BN0_WF_LPON_TOP_BASE + 0x2c8) // B2C8
#define BN0_WF_LPON_TOP_MUEDCA13TR_ADDR                        (BN0_WF_LPON_TOP_BASE + 0x2cc) // B2CC
#define BN0_WF_LPON_TOP_MUEDCA14TR_ADDR                        (BN0_WF_LPON_TOP_BASE + 0x2d0) // B2D0
#define BN0_WF_LPON_TOP_MUEDCA15TR_ADDR                        (BN0_WF_LPON_TOP_BASE + 0x2d4) // B2D4
#define BN0_WF_LPON_TOP_TXTCR0_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x2d8) // B2D8
#define BN0_WF_LPON_TOP_TXTCR1_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x2dc) // B2DC
#define BN0_WF_LPON_TOP_TXTCR2_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x2e0) // B2E0
#define BN0_WF_LPON_TOP_TXTCR3_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x2e4) // B2E4
#define BN0_WF_LPON_TOP_MPTCR0_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x02e8) // B2E8
#define BN0_WF_LPON_TOP_MPTCR2_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x2ec) // B2EC
#define BN0_WF_LPON_TOP_MPTCR4_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x2f0) // B2F0
#define BN0_WF_LPON_TOP_MPTCR6_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x2f4) // B2F4
#define BN0_WF_LPON_TOP_MPTCR8_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x2f8) // B2F8
#define BN0_WF_LPON_TOP_DUMMY1_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x2fc) // B2FC
#define BN0_WF_LPON_TOP_MPTCR1_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x300) // B300
#define BN0_WF_LPON_TOP_MPTCR3_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x304) // B304
#define BN0_WF_LPON_TOP_MPTCR5_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x308) // B308
#define BN0_WF_LPON_TOP_MPTCR7_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x30c) // B30C
#define BN0_WF_LPON_TOP_MPTCR9_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x310) // B310
#define BN0_WF_LPON_TOP_FRCR_ADDR                              (BN0_WF_LPON_TOP_BASE + 0x0314) // B314
#define BN0_WF_LPON_TOP_MMCR0_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x318) // B318
#define BN0_WF_LPON_TOP_MMCR1_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x31c) // B31C
#define BN0_WF_LPON_TOP_MMCR2_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x320) // B320
#define BN0_WF_LPON_TOP_MMCR3_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x324) // B324
#define BN0_WF_LPON_TOP_MMBSR0_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x328) // B328
#define BN0_WF_LPON_TOP_MMBSR1_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x32c) // B32C
#define BN0_WF_LPON_TOP_MMCR4_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x330) // B330
#define BN0_WF_LPON_TOP_MMCR5_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x334) // B334
#define BN0_WF_LPON_TOP_MMCR6_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x338) // B338
#define BN0_WF_LPON_TOP_MMCR7_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x33c) // B33C
#define BN0_WF_LPON_TOP_MMBSR2_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x340) // B340
#define BN0_WF_LPON_TOP_MMBSR3_ADDR                            (BN0_WF_LPON_TOP_BASE + 0x344) // B344
#define BN0_WF_LPON_TOP_QCCR0_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x348) // B348
#define BN0_WF_LPON_TOP_QCCR1_ADDR                             (BN0_WF_LPON_TOP_BASE + 0x34c) // B34C




/* =====================================================================================

  ---TT0SBOR1 (0x820EB000 + 0x000)---

    TTTT0_SBOFFSET1[17..0]       - (RW) Indicates TTTT0 (Target TIM Transmission Time) Sub BSSID offset 1 of TTTT0
                                     Unit: 1us
                                     Range: -131072~131071us
    RESERVED18[28..18]           - (RO) Reserved bits
    SBSS_TTTT0_TSF0_EN[29]       - (RW) Enable Sub-BSS TTTT0_x function (x=1~15)
                                     Set it to 1 if any of Sub-BSS TTTT0_x is enabled.
    TTTT0_1_INT_EN[30]           - (RW) Enables  TTTT0_1 INT
    PRE_TTTT0_1_INT_EN[31]       - (RW) Enables PRE_TTTT0_1 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SBOR1_PRE_TTTT0_1_INT_EN_ADDR       BN0_WF_LPON_TOP_TT0SBOR1_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR1_PRE_TTTT0_1_INT_EN_MASK       0x80000000                // PRE_TTTT0_1_INT_EN[31]
#define BN0_WF_LPON_TOP_TT0SBOR1_PRE_TTTT0_1_INT_EN_SHFT       31
#define BN0_WF_LPON_TOP_TT0SBOR1_TTTT0_1_INT_EN_ADDR           BN0_WF_LPON_TOP_TT0SBOR1_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR1_TTTT0_1_INT_EN_MASK           0x40000000                // TTTT0_1_INT_EN[30]
#define BN0_WF_LPON_TOP_TT0SBOR1_TTTT0_1_INT_EN_SHFT           30
#define BN0_WF_LPON_TOP_TT0SBOR1_SBSS_TTTT0_TSF0_EN_ADDR       BN0_WF_LPON_TOP_TT0SBOR1_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR1_SBSS_TTTT0_TSF0_EN_MASK       0x20000000                // SBSS_TTTT0_TSF0_EN[29]
#define BN0_WF_LPON_TOP_TT0SBOR1_SBSS_TTTT0_TSF0_EN_SHFT       29
#define BN0_WF_LPON_TOP_TT0SBOR1_TTTT0_SBOFFSET1_ADDR          BN0_WF_LPON_TOP_TT0SBOR1_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR1_TTTT0_SBOFFSET1_MASK          0x0003FFFF                // TTTT0_SBOFFSET1[17..0]
#define BN0_WF_LPON_TOP_TT0SBOR1_TTTT0_SBOFFSET1_SHFT          0

/* =====================================================================================

  ---TT0SBOR2 (0x820EB000 + 0x004)---

    TTTT0_SBOFFSET2[17..0]       - (RW) Indicates TTTT0 (Target TIM Transmission Time) Sub BSSID offset 2 of TTTT0
                                     Unit: 1us
                                     Range: -131072~131071us
    RESERVED18[29..18]           - (RO) Reserved bits
    TTTT0_2_INT_EN[30]           - (RW) Enables TTTT0_2 INT
    PRE_TTTT0_2_INT_EN[31]       - (RW) Enables PRE_TTTT0_2 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SBOR2_PRE_TTTT0_2_INT_EN_ADDR       BN0_WF_LPON_TOP_TT0SBOR2_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR2_PRE_TTTT0_2_INT_EN_MASK       0x80000000                // PRE_TTTT0_2_INT_EN[31]
#define BN0_WF_LPON_TOP_TT0SBOR2_PRE_TTTT0_2_INT_EN_SHFT       31
#define BN0_WF_LPON_TOP_TT0SBOR2_TTTT0_2_INT_EN_ADDR           BN0_WF_LPON_TOP_TT0SBOR2_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR2_TTTT0_2_INT_EN_MASK           0x40000000                // TTTT0_2_INT_EN[30]
#define BN0_WF_LPON_TOP_TT0SBOR2_TTTT0_2_INT_EN_SHFT           30
#define BN0_WF_LPON_TOP_TT0SBOR2_TTTT0_SBOFFSET2_ADDR          BN0_WF_LPON_TOP_TT0SBOR2_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR2_TTTT0_SBOFFSET2_MASK          0x0003FFFF                // TTTT0_SBOFFSET2[17..0]
#define BN0_WF_LPON_TOP_TT0SBOR2_TTTT0_SBOFFSET2_SHFT          0

/* =====================================================================================

  ---TT0SBOR3 (0x820EB000 + 0x008)---

    TTTT0_SBOFFSET3[17..0]       - (RW) Indicates TTTT0 (Target TIM Transmission Time) Sub BSSID offset 3 of TTTT0
                                     Unit: 1us
                                     Range: -131072~131071us
    RESERVED18[29..18]           - (RO) Reserved bits
    TTTT0_3_INT_EN[30]           - (RW) Enables TTTT0_3 INT
    PRE_TTTT0_3_INT_EN[31]       - (RW) Enables PRE_TTTT0_3 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SBOR3_PRE_TTTT0_3_INT_EN_ADDR       BN0_WF_LPON_TOP_TT0SBOR3_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR3_PRE_TTTT0_3_INT_EN_MASK       0x80000000                // PRE_TTTT0_3_INT_EN[31]
#define BN0_WF_LPON_TOP_TT0SBOR3_PRE_TTTT0_3_INT_EN_SHFT       31
#define BN0_WF_LPON_TOP_TT0SBOR3_TTTT0_3_INT_EN_ADDR           BN0_WF_LPON_TOP_TT0SBOR3_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR3_TTTT0_3_INT_EN_MASK           0x40000000                // TTTT0_3_INT_EN[30]
#define BN0_WF_LPON_TOP_TT0SBOR3_TTTT0_3_INT_EN_SHFT           30
#define BN0_WF_LPON_TOP_TT0SBOR3_TTTT0_SBOFFSET3_ADDR          BN0_WF_LPON_TOP_TT0SBOR3_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR3_TTTT0_SBOFFSET3_MASK          0x0003FFFF                // TTTT0_SBOFFSET3[17..0]
#define BN0_WF_LPON_TOP_TT0SBOR3_TTTT0_SBOFFSET3_SHFT          0

/* =====================================================================================

  ---TT0SBOR4 (0x820EB000 + 0x00c)---

    TTTT0_SBOFFSET4[17..0]       - (RW) Indicates TTTT0 (Target TIM Transmission Time) Sub BSSID offset 4 of TTTT0
                                     Unit: 1us
                                     Range: -131072~131071us
    RESERVED18[29..18]           - (RO) Reserved bits
    TTTT0_4_INT_EN[30]           - (RW) Enables TTTT0_4 INT
    PRE_TTTT0_4_INT_EN[31]       - (RW) Enables PRE_TTTT0_4 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SBOR4_PRE_TTTT0_4_INT_EN_ADDR       BN0_WF_LPON_TOP_TT0SBOR4_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR4_PRE_TTTT0_4_INT_EN_MASK       0x80000000                // PRE_TTTT0_4_INT_EN[31]
#define BN0_WF_LPON_TOP_TT0SBOR4_PRE_TTTT0_4_INT_EN_SHFT       31
#define BN0_WF_LPON_TOP_TT0SBOR4_TTTT0_4_INT_EN_ADDR           BN0_WF_LPON_TOP_TT0SBOR4_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR4_TTTT0_4_INT_EN_MASK           0x40000000                // TTTT0_4_INT_EN[30]
#define BN0_WF_LPON_TOP_TT0SBOR4_TTTT0_4_INT_EN_SHFT           30
#define BN0_WF_LPON_TOP_TT0SBOR4_TTTT0_SBOFFSET4_ADDR          BN0_WF_LPON_TOP_TT0SBOR4_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR4_TTTT0_SBOFFSET4_MASK          0x0003FFFF                // TTTT0_SBOFFSET4[17..0]
#define BN0_WF_LPON_TOP_TT0SBOR4_TTTT0_SBOFFSET4_SHFT          0

/* =====================================================================================

  ---TT0SBOR5 (0x820EB000 + 0x010)---

    TTTT0_SBOFFSET5[17..0]       - (RW) Indicates TTTT0 (Target TIM Transmission Time) Sub BSSID offset 5 of TTTT0
                                     Unit: 1us
                                     Range: 131072~131071us
    RESERVED18[29..18]           - (RO) Reserved bits
    TTTT0_5_INT_EN[30]           - (RW) Enables TTTT0_5 INT
    PRE_TTTT0_5_INT_EN[31]       - (RW) Enables PRE_TTTT0_5 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SBOR5_PRE_TTTT0_5_INT_EN_ADDR       BN0_WF_LPON_TOP_TT0SBOR5_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR5_PRE_TTTT0_5_INT_EN_MASK       0x80000000                // PRE_TTTT0_5_INT_EN[31]
#define BN0_WF_LPON_TOP_TT0SBOR5_PRE_TTTT0_5_INT_EN_SHFT       31
#define BN0_WF_LPON_TOP_TT0SBOR5_TTTT0_5_INT_EN_ADDR           BN0_WF_LPON_TOP_TT0SBOR5_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR5_TTTT0_5_INT_EN_MASK           0x40000000                // TTTT0_5_INT_EN[30]
#define BN0_WF_LPON_TOP_TT0SBOR5_TTTT0_5_INT_EN_SHFT           30
#define BN0_WF_LPON_TOP_TT0SBOR5_TTTT0_SBOFFSET5_ADDR          BN0_WF_LPON_TOP_TT0SBOR5_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR5_TTTT0_SBOFFSET5_MASK          0x0003FFFF                // TTTT0_SBOFFSET5[17..0]
#define BN0_WF_LPON_TOP_TT0SBOR5_TTTT0_SBOFFSET5_SHFT          0

/* =====================================================================================

  ---TT0SBOR6 (0x820EB000 + 0x014)---

    TTTT0_SBOFFSET6[17..0]       - (RW) Indicates TTTT0 (Target TIM Transmission Time) Sub BSSID offset 6 of TTTT0
                                     Unit: 1us
                                     Range: 131072~131071us
    RESERVED18[29..18]           - (RO) Reserved bits
    TTTT0_6_INT_EN[30]           - (RW) Enables TTTT0_6 INT
    PRE_TTTT0_6_INT_EN[31]       - (RW) Enables PRE_TTTT0_6 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SBOR6_PRE_TTTT0_6_INT_EN_ADDR       BN0_WF_LPON_TOP_TT0SBOR6_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR6_PRE_TTTT0_6_INT_EN_MASK       0x80000000                // PRE_TTTT0_6_INT_EN[31]
#define BN0_WF_LPON_TOP_TT0SBOR6_PRE_TTTT0_6_INT_EN_SHFT       31
#define BN0_WF_LPON_TOP_TT0SBOR6_TTTT0_6_INT_EN_ADDR           BN0_WF_LPON_TOP_TT0SBOR6_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR6_TTTT0_6_INT_EN_MASK           0x40000000                // TTTT0_6_INT_EN[30]
#define BN0_WF_LPON_TOP_TT0SBOR6_TTTT0_6_INT_EN_SHFT           30
#define BN0_WF_LPON_TOP_TT0SBOR6_TTTT0_SBOFFSET6_ADDR          BN0_WF_LPON_TOP_TT0SBOR6_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR6_TTTT0_SBOFFSET6_MASK          0x0003FFFF                // TTTT0_SBOFFSET6[17..0]
#define BN0_WF_LPON_TOP_TT0SBOR6_TTTT0_SBOFFSET6_SHFT          0

/* =====================================================================================

  ---TT0SBOR7 (0x820EB000 + 0x018)---

    TTTT0_SBOFFSET7[17..0]       - (RW) Indicates TTTT0 (Target TIM Transmission Time) Sub BSSID offset 7 of TTTT0
                                     Unit: 1us
                                     Range: -131072~131071us
    RESERVED18[29..18]           - (RO) Reserved bits
    TTTT0_7_INT_EN[30]           - (RW) Enables TTTT0_7 INT
    PRE_TTTT0_7_INT_EN[31]       - (RW) Enables PRE_TTTT0_7 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SBOR7_PRE_TTTT0_7_INT_EN_ADDR       BN0_WF_LPON_TOP_TT0SBOR7_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR7_PRE_TTTT0_7_INT_EN_MASK       0x80000000                // PRE_TTTT0_7_INT_EN[31]
#define BN0_WF_LPON_TOP_TT0SBOR7_PRE_TTTT0_7_INT_EN_SHFT       31
#define BN0_WF_LPON_TOP_TT0SBOR7_TTTT0_7_INT_EN_ADDR           BN0_WF_LPON_TOP_TT0SBOR7_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR7_TTTT0_7_INT_EN_MASK           0x40000000                // TTTT0_7_INT_EN[30]
#define BN0_WF_LPON_TOP_TT0SBOR7_TTTT0_7_INT_EN_SHFT           30
#define BN0_WF_LPON_TOP_TT0SBOR7_TTTT0_SBOFFSET7_ADDR          BN0_WF_LPON_TOP_TT0SBOR7_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR7_TTTT0_SBOFFSET7_MASK          0x0003FFFF                // TTTT0_SBOFFSET7[17..0]
#define BN0_WF_LPON_TOP_TT0SBOR7_TTTT0_SBOFFSET7_SHFT          0

/* =====================================================================================

  ---TT0SBOR8 (0x820EB000 + 0x01c)---

    TTTT0_SBOFFSET8[17..0]       - (RW) Indicates TTTT0 (Target TIM Transmission Time) Sub BSSID offset 8 of TTTT0
                                     Unit: 1us
                                     Range: -131072~131071us
    RESERVED18[29..18]           - (RO) Reserved bits
    TTTT0_8_INT_EN[30]           - (RW) Enables TTTT0_8 INT
    PRE_TTTT0_8_INT_EN[31]       - (RW) Enables PRE_TTTT0_8 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SBOR8_PRE_TTTT0_8_INT_EN_ADDR       BN0_WF_LPON_TOP_TT0SBOR8_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR8_PRE_TTTT0_8_INT_EN_MASK       0x80000000                // PRE_TTTT0_8_INT_EN[31]
#define BN0_WF_LPON_TOP_TT0SBOR8_PRE_TTTT0_8_INT_EN_SHFT       31
#define BN0_WF_LPON_TOP_TT0SBOR8_TTTT0_8_INT_EN_ADDR           BN0_WF_LPON_TOP_TT0SBOR8_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR8_TTTT0_8_INT_EN_MASK           0x40000000                // TTTT0_8_INT_EN[30]
#define BN0_WF_LPON_TOP_TT0SBOR8_TTTT0_8_INT_EN_SHFT           30
#define BN0_WF_LPON_TOP_TT0SBOR8_TTTT0_SBOFFSET8_ADDR          BN0_WF_LPON_TOP_TT0SBOR8_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR8_TTTT0_SBOFFSET8_MASK          0x0003FFFF                // TTTT0_SBOFFSET8[17..0]
#define BN0_WF_LPON_TOP_TT0SBOR8_TTTT0_SBOFFSET8_SHFT          0

/* =====================================================================================

  ---TT0SBOR9 (0x820EB000 + 0x020)---

    TTTT0_SBOFFSET9[17..0]       - (RW) Indicates TTTT0 (Target TIM Transmission Time) Sub BSSID offset 9 of TTTT0
                                     Unit: 1us
                                     Range: -131092~131091us
    RESERVED18[29..18]           - (RO) Reserved bits
    TTTT0_9_INT_EN[30]           - (RW) Enables TTTT0_9 INT
    PRE_TTTT0_9_INT_EN[31]       - (RW) Enables PRE_TTTT0_9 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SBOR9_PRE_TTTT0_9_INT_EN_ADDR       BN0_WF_LPON_TOP_TT0SBOR9_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR9_PRE_TTTT0_9_INT_EN_MASK       0x80000000                // PRE_TTTT0_9_INT_EN[31]
#define BN0_WF_LPON_TOP_TT0SBOR9_PRE_TTTT0_9_INT_EN_SHFT       31
#define BN0_WF_LPON_TOP_TT0SBOR9_TTTT0_9_INT_EN_ADDR           BN0_WF_LPON_TOP_TT0SBOR9_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR9_TTTT0_9_INT_EN_MASK           0x40000000                // TTTT0_9_INT_EN[30]
#define BN0_WF_LPON_TOP_TT0SBOR9_TTTT0_9_INT_EN_SHFT           30
#define BN0_WF_LPON_TOP_TT0SBOR9_TTTT0_SBOFFSET9_ADDR          BN0_WF_LPON_TOP_TT0SBOR9_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR9_TTTT0_SBOFFSET9_MASK          0x0003FFFF                // TTTT0_SBOFFSET9[17..0]
#define BN0_WF_LPON_TOP_TT0SBOR9_TTTT0_SBOFFSET9_SHFT          0

/* =====================================================================================

  ---TT0SBOR10 (0x820EB000 + 0x024)---

    TTTT0_SBOFFSET10[17..0]      - (RW) Indicates TTTT0 (Target TIM Transmission Time) Sub BSSID offset 10 of TTTT0
                                     Unit: 1us
                                     Range: -131072~131071us
    RESERVED18[29..18]           - (RO) Reserved bits
    TTTT0_10_INT_EN[30]          - (RW) Enables TTTT0_10 INT
    PRE_TTTT0_10_INT_EN[31]      - (RW) Enables PRE_TTTT0_10 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SBOR10_PRE_TTTT0_10_INT_EN_ADDR     BN0_WF_LPON_TOP_TT0SBOR10_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR10_PRE_TTTT0_10_INT_EN_MASK     0x80000000                // PRE_TTTT0_10_INT_EN[31]
#define BN0_WF_LPON_TOP_TT0SBOR10_PRE_TTTT0_10_INT_EN_SHFT     31
#define BN0_WF_LPON_TOP_TT0SBOR10_TTTT0_10_INT_EN_ADDR         BN0_WF_LPON_TOP_TT0SBOR10_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR10_TTTT0_10_INT_EN_MASK         0x40000000                // TTTT0_10_INT_EN[30]
#define BN0_WF_LPON_TOP_TT0SBOR10_TTTT0_10_INT_EN_SHFT         30
#define BN0_WF_LPON_TOP_TT0SBOR10_TTTT0_SBOFFSET10_ADDR        BN0_WF_LPON_TOP_TT0SBOR10_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR10_TTTT0_SBOFFSET10_MASK        0x0003FFFF                // TTTT0_SBOFFSET10[17..0]
#define BN0_WF_LPON_TOP_TT0SBOR10_TTTT0_SBOFFSET10_SHFT        0

/* =====================================================================================

  ---TT0SBOR11 (0x820EB000 + 0x028)---

    TTTT0_SBOFFSET11[17..0]      - (RW) Indicates TTTT0 (Target TIM Transmission Time) Sub BSSID offset 11 of TTTT0
                                     Unit: 1us
                                     Range: -131072~131071us
    RESERVED18[29..18]           - (RO) Reserved bits
    TTTT0_11_INT_EN[30]          - (RW) Enables TTTT0_11 INT
    PRE_TTTT0_11_INT_EN[31]      - (RW) Enables PRE_TTTT0_11 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SBOR11_PRE_TTTT0_11_INT_EN_ADDR     BN0_WF_LPON_TOP_TT0SBOR11_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR11_PRE_TTTT0_11_INT_EN_MASK     0x80000000                // PRE_TTTT0_11_INT_EN[31]
#define BN0_WF_LPON_TOP_TT0SBOR11_PRE_TTTT0_11_INT_EN_SHFT     31
#define BN0_WF_LPON_TOP_TT0SBOR11_TTTT0_11_INT_EN_ADDR         BN0_WF_LPON_TOP_TT0SBOR11_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR11_TTTT0_11_INT_EN_MASK         0x40000000                // TTTT0_11_INT_EN[30]
#define BN0_WF_LPON_TOP_TT0SBOR11_TTTT0_11_INT_EN_SHFT         30
#define BN0_WF_LPON_TOP_TT0SBOR11_TTTT0_SBOFFSET11_ADDR        BN0_WF_LPON_TOP_TT0SBOR11_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR11_TTTT0_SBOFFSET11_MASK        0x0003FFFF                // TTTT0_SBOFFSET11[17..0]
#define BN0_WF_LPON_TOP_TT0SBOR11_TTTT0_SBOFFSET11_SHFT        0

/* =====================================================================================

  ---TT0SBOR12 (0x820EB000 + 0x02c)---

    TTTT0_SBOFFSET12[17..0]      - (RW) Indicates TTTT0 (Target TIM Transmission Time) Sub BSSID offset 12 of TTTT0
                                     Unit: 1us
                                     Range: -131072~131071us
    RESERVED18[29..18]           - (RO) Reserved bits
    TTTT0_12_INT_EN[30]          - (RW) Enables TTTT0_12 INT
    PRE_TTTT0_12_INT_EN[31]      - (RW) Enables PRE_TTTT0_12 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SBOR12_PRE_TTTT0_12_INT_EN_ADDR     BN0_WF_LPON_TOP_TT0SBOR12_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR12_PRE_TTTT0_12_INT_EN_MASK     0x80000000                // PRE_TTTT0_12_INT_EN[31]
#define BN0_WF_LPON_TOP_TT0SBOR12_PRE_TTTT0_12_INT_EN_SHFT     31
#define BN0_WF_LPON_TOP_TT0SBOR12_TTTT0_12_INT_EN_ADDR         BN0_WF_LPON_TOP_TT0SBOR12_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR12_TTTT0_12_INT_EN_MASK         0x40000000                // TTTT0_12_INT_EN[30]
#define BN0_WF_LPON_TOP_TT0SBOR12_TTTT0_12_INT_EN_SHFT         30
#define BN0_WF_LPON_TOP_TT0SBOR12_TTTT0_SBOFFSET12_ADDR        BN0_WF_LPON_TOP_TT0SBOR12_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR12_TTTT0_SBOFFSET12_MASK        0x0003FFFF                // TTTT0_SBOFFSET12[17..0]
#define BN0_WF_LPON_TOP_TT0SBOR12_TTTT0_SBOFFSET12_SHFT        0

/* =====================================================================================

  ---TT0SBOR13 (0x820EB000 + 0x030)---

    TTTT0_SBOFFSET13[17..0]      - (RW) Indicates TTTT0 (Target TIM Transmission Time) Sub BSSID offset 13 of TTTT0
                                     Unit: 1us
                                     Range: -131072~131071us
    RESERVED18[29..18]           - (RO) Reserved bits
    TTTT0_13_INT_EN[30]          - (RW) Enables TTTT0_13 INT
    PRE_TTTT0_13_INT_EN[31]      - (RW) Enables PRE_TTTT0_13 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SBOR13_PRE_TTTT0_13_INT_EN_ADDR     BN0_WF_LPON_TOP_TT0SBOR13_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR13_PRE_TTTT0_13_INT_EN_MASK     0x80000000                // PRE_TTTT0_13_INT_EN[31]
#define BN0_WF_LPON_TOP_TT0SBOR13_PRE_TTTT0_13_INT_EN_SHFT     31
#define BN0_WF_LPON_TOP_TT0SBOR13_TTTT0_13_INT_EN_ADDR         BN0_WF_LPON_TOP_TT0SBOR13_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR13_TTTT0_13_INT_EN_MASK         0x40000000                // TTTT0_13_INT_EN[30]
#define BN0_WF_LPON_TOP_TT0SBOR13_TTTT0_13_INT_EN_SHFT         30
#define BN0_WF_LPON_TOP_TT0SBOR13_TTTT0_SBOFFSET13_ADDR        BN0_WF_LPON_TOP_TT0SBOR13_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR13_TTTT0_SBOFFSET13_MASK        0x0003FFFF                // TTTT0_SBOFFSET13[17..0]
#define BN0_WF_LPON_TOP_TT0SBOR13_TTTT0_SBOFFSET13_SHFT        0

/* =====================================================================================

  ---TT0SBOR14 (0x820EB000 + 0x034)---

    TTTT0_SBOFFSET14[17..0]      - (RW) Indicates TTTT0 (Target TIM Transmission Time) Sub BSSID offset 14 of TTTT0
                                     Unit: 1us
                                     Range: -131072~131071us
    RESERVED18[29..18]           - (RO) Reserved bits
    TTTT0_14_INT_EN[30]          - (RW) Enables TTTT0_14 INT
    PRE_TTTT0_14_INT_EN[31]      - (RW) Enables PRE_TTTT0_14 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SBOR14_PRE_TTTT0_14_INT_EN_ADDR     BN0_WF_LPON_TOP_TT0SBOR14_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR14_PRE_TTTT0_14_INT_EN_MASK     0x80000000                // PRE_TTTT0_14_INT_EN[31]
#define BN0_WF_LPON_TOP_TT0SBOR14_PRE_TTTT0_14_INT_EN_SHFT     31
#define BN0_WF_LPON_TOP_TT0SBOR14_TTTT0_14_INT_EN_ADDR         BN0_WF_LPON_TOP_TT0SBOR14_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR14_TTTT0_14_INT_EN_MASK         0x40000000                // TTTT0_14_INT_EN[30]
#define BN0_WF_LPON_TOP_TT0SBOR14_TTTT0_14_INT_EN_SHFT         30
#define BN0_WF_LPON_TOP_TT0SBOR14_TTTT0_SBOFFSET14_ADDR        BN0_WF_LPON_TOP_TT0SBOR14_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR14_TTTT0_SBOFFSET14_MASK        0x0003FFFF                // TTTT0_SBOFFSET14[17..0]
#define BN0_WF_LPON_TOP_TT0SBOR14_TTTT0_SBOFFSET14_SHFT        0

/* =====================================================================================

  ---TT0SBOR15 (0x820EB000 + 0x038)---

    TTTT0_SBOFFSET15[17..0]      - (RW) Indicates TTTT0 (Target TIM Transmission Time) Sub BSSID offset 15 of TTTT0
                                     Unit: 1us
                                     Range: -131072~131071us
    RESERVED18[29..18]           - (RO) Reserved bits
    TTTT0_15_INT_EN[30]          - (RW) Enables TTTT0_15 INT
    PRE_TTTT0_15_INT_EN[31]      - (RW) Enables PRE_TTTT0_15 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SBOR15_PRE_TTTT0_15_INT_EN_ADDR     BN0_WF_LPON_TOP_TT0SBOR15_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR15_PRE_TTTT0_15_INT_EN_MASK     0x80000000                // PRE_TTTT0_15_INT_EN[31]
#define BN0_WF_LPON_TOP_TT0SBOR15_PRE_TTTT0_15_INT_EN_SHFT     31
#define BN0_WF_LPON_TOP_TT0SBOR15_TTTT0_15_INT_EN_ADDR         BN0_WF_LPON_TOP_TT0SBOR15_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR15_TTTT0_15_INT_EN_MASK         0x40000000                // TTTT0_15_INT_EN[30]
#define BN0_WF_LPON_TOP_TT0SBOR15_TTTT0_15_INT_EN_SHFT         30
#define BN0_WF_LPON_TOP_TT0SBOR15_TTTT0_SBOFFSET15_ADDR        BN0_WF_LPON_TOP_TT0SBOR15_ADDR
#define BN0_WF_LPON_TOP_TT0SBOR15_TTTT0_SBOFFSET15_MASK        0x0003FFFF                // TTTT0_SBOFFSET15[17..0]
#define BN0_WF_LPON_TOP_TT0SBOR15_TTTT0_SBOFFSET15_SHFT        0

/* =====================================================================================

  ---SBTOR1 (0x820EB000 + 0x03c)---

    SUB_BSSID0_TIME_OFFSET_1[19..0] - (RW) SUB BSSID time offset Value0 which includes n*(SIFS+ TxBcnTime) for TSF0, (n=1)
                                     It is used as infra-AP transmits Beacon by a SIFS burst continuously. HW will use the current TSF minus the offset value to prevent STA from waking up on the next TBTT to save more power.
    RESERVED20[28..20]           - (RO) Reserved bits
    SBSS_TBTT0_TSF0_EN[29]       - (RW) Enables Sub-BSS TBTT0_x function (x=1~15)
                                     Set it to 1 if any of Sub-BSS TBTT0_x is enabled.
    TBTT0_1_INT_EN[30]           - (RW) Enables TBTT0_1 INT
    PRE_TBTT0_1_INT_EN[31]       - (RW) Enables PRE_TBTT0_1 INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOR1_PRE_TBTT0_1_INT_EN_ADDR         BN0_WF_LPON_TOP_SBTOR1_ADDR
#define BN0_WF_LPON_TOP_SBTOR1_PRE_TBTT0_1_INT_EN_MASK         0x80000000                // PRE_TBTT0_1_INT_EN[31]
#define BN0_WF_LPON_TOP_SBTOR1_PRE_TBTT0_1_INT_EN_SHFT         31
#define BN0_WF_LPON_TOP_SBTOR1_TBTT0_1_INT_EN_ADDR             BN0_WF_LPON_TOP_SBTOR1_ADDR
#define BN0_WF_LPON_TOP_SBTOR1_TBTT0_1_INT_EN_MASK             0x40000000                // TBTT0_1_INT_EN[30]
#define BN0_WF_LPON_TOP_SBTOR1_TBTT0_1_INT_EN_SHFT             30
#define BN0_WF_LPON_TOP_SBTOR1_SBSS_TBTT0_TSF0_EN_ADDR         BN0_WF_LPON_TOP_SBTOR1_ADDR
#define BN0_WF_LPON_TOP_SBTOR1_SBSS_TBTT0_TSF0_EN_MASK         0x20000000                // SBSS_TBTT0_TSF0_EN[29]
#define BN0_WF_LPON_TOP_SBTOR1_SBSS_TBTT0_TSF0_EN_SHFT         29
#define BN0_WF_LPON_TOP_SBTOR1_SUB_BSSID0_TIME_OFFSET_1_ADDR   BN0_WF_LPON_TOP_SBTOR1_ADDR
#define BN0_WF_LPON_TOP_SBTOR1_SUB_BSSID0_TIME_OFFSET_1_MASK   0x000FFFFF                // SUB_BSSID0_TIME_OFFSET_1[19..0]
#define BN0_WF_LPON_TOP_SBTOR1_SUB_BSSID0_TIME_OFFSET_1_SHFT   0

/* =====================================================================================

  ---SBTOR2 (0x820EB000 + 0x040)---

    SUB_BSSID0_TIME_OFFSET_2[19..0] - (RW) Same as SUB BSSID time offset Value0 which includes n*(SIFS+ T2BcnTime) for TSF0, (n=2)
    RESERVED20[29..20]           - (RO) Reserved bits
    TBTT0_2_INT_EN[30]           - (RW) Enables TBTT0_2 INT
    PRE_TBTT0_x_INT_EN[31]       - (RW) Enables PRE_TBTT0_x INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOR2_PRE_TBTT0_x_INT_EN_ADDR         BN0_WF_LPON_TOP_SBTOR2_ADDR
#define BN0_WF_LPON_TOP_SBTOR2_PRE_TBTT0_x_INT_EN_MASK         0x80000000                // PRE_TBTT0_x_INT_EN[31]
#define BN0_WF_LPON_TOP_SBTOR2_PRE_TBTT0_x_INT_EN_SHFT         31
#define BN0_WF_LPON_TOP_SBTOR2_TBTT0_2_INT_EN_ADDR             BN0_WF_LPON_TOP_SBTOR2_ADDR
#define BN0_WF_LPON_TOP_SBTOR2_TBTT0_2_INT_EN_MASK             0x40000000                // TBTT0_2_INT_EN[30]
#define BN0_WF_LPON_TOP_SBTOR2_TBTT0_2_INT_EN_SHFT             30
#define BN0_WF_LPON_TOP_SBTOR2_SUB_BSSID0_TIME_OFFSET_2_ADDR   BN0_WF_LPON_TOP_SBTOR2_ADDR
#define BN0_WF_LPON_TOP_SBTOR2_SUB_BSSID0_TIME_OFFSET_2_MASK   0x000FFFFF                // SUB_BSSID0_TIME_OFFSET_2[19..0]
#define BN0_WF_LPON_TOP_SBTOR2_SUB_BSSID0_TIME_OFFSET_2_SHFT   0

/* =====================================================================================

  ---SBTOR3 (0x820EB000 + 0x044)---

    SUB_BSSID0_TIME_OFFSET_3[19..0] - (RW) Same as SUB BSSID time offset Value0 which includes n*(SIFS+ T3BcnTime) for TSF0, (n=3)
    RESERVED20[29..20]           - (RO) Reserved bits
    TBTT0_3_INT_EN[30]           - (RW) Enables TBTT0_3 INT
    PRE_TBTT0_x_INT_EN[31]       - (RW) Enables PRE_TBTT0_x INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOR3_PRE_TBTT0_x_INT_EN_ADDR         BN0_WF_LPON_TOP_SBTOR3_ADDR
#define BN0_WF_LPON_TOP_SBTOR3_PRE_TBTT0_x_INT_EN_MASK         0x80000000                // PRE_TBTT0_x_INT_EN[31]
#define BN0_WF_LPON_TOP_SBTOR3_PRE_TBTT0_x_INT_EN_SHFT         31
#define BN0_WF_LPON_TOP_SBTOR3_TBTT0_3_INT_EN_ADDR             BN0_WF_LPON_TOP_SBTOR3_ADDR
#define BN0_WF_LPON_TOP_SBTOR3_TBTT0_3_INT_EN_MASK             0x40000000                // TBTT0_3_INT_EN[30]
#define BN0_WF_LPON_TOP_SBTOR3_TBTT0_3_INT_EN_SHFT             30
#define BN0_WF_LPON_TOP_SBTOR3_SUB_BSSID0_TIME_OFFSET_3_ADDR   BN0_WF_LPON_TOP_SBTOR3_ADDR
#define BN0_WF_LPON_TOP_SBTOR3_SUB_BSSID0_TIME_OFFSET_3_MASK   0x000FFFFF                // SUB_BSSID0_TIME_OFFSET_3[19..0]
#define BN0_WF_LPON_TOP_SBTOR3_SUB_BSSID0_TIME_OFFSET_3_SHFT   0

/* =====================================================================================

  ---SBTOR4 (0x820EB000 + 0x048)---

    SUB_BSSID0_TIME_OFFSET_4[19..0] - (RW) Same as SUB BSSID time offset Value0 which includes n*(SIFS+ T4BcnTime) for TSF0, (n=4)
    RESERVED20[29..20]           - (RO) Reserved bits
    TBTT0_4_INT_EN[30]           - (RW) Enables TBTT0_4 INT
    PRE_TBTT0_x_INT_EN[31]       - (RW) Enables PRE_TBTT0_x INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOR4_PRE_TBTT0_x_INT_EN_ADDR         BN0_WF_LPON_TOP_SBTOR4_ADDR
#define BN0_WF_LPON_TOP_SBTOR4_PRE_TBTT0_x_INT_EN_MASK         0x80000000                // PRE_TBTT0_x_INT_EN[31]
#define BN0_WF_LPON_TOP_SBTOR4_PRE_TBTT0_x_INT_EN_SHFT         31
#define BN0_WF_LPON_TOP_SBTOR4_TBTT0_4_INT_EN_ADDR             BN0_WF_LPON_TOP_SBTOR4_ADDR
#define BN0_WF_LPON_TOP_SBTOR4_TBTT0_4_INT_EN_MASK             0x40000000                // TBTT0_4_INT_EN[30]
#define BN0_WF_LPON_TOP_SBTOR4_TBTT0_4_INT_EN_SHFT             30
#define BN0_WF_LPON_TOP_SBTOR4_SUB_BSSID0_TIME_OFFSET_4_ADDR   BN0_WF_LPON_TOP_SBTOR4_ADDR
#define BN0_WF_LPON_TOP_SBTOR4_SUB_BSSID0_TIME_OFFSET_4_MASK   0x000FFFFF                // SUB_BSSID0_TIME_OFFSET_4[19..0]
#define BN0_WF_LPON_TOP_SBTOR4_SUB_BSSID0_TIME_OFFSET_4_SHFT   0

/* =====================================================================================

  ---SBTOR5 (0x820EB000 + 0x04c)---

    SUB_BSSID0_TIME_OFFSET_5[19..0] - (RW) Same as SUB BSSID time offset Value0 which includes n*(SIFS+ T5BcnTime) for TSF0, (n=5)
    RESERVED20[29..20]           - (RO) Reserved bits
    TBTT0_5_INT_EN[30]           - (RW) Enables TBTT0_5 INT
    PRE_TBTT0_x_INT_EN[31]       - (RW) Enables PRE_TBTT0_x INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOR5_PRE_TBTT0_x_INT_EN_ADDR         BN0_WF_LPON_TOP_SBTOR5_ADDR
#define BN0_WF_LPON_TOP_SBTOR5_PRE_TBTT0_x_INT_EN_MASK         0x80000000                // PRE_TBTT0_x_INT_EN[31]
#define BN0_WF_LPON_TOP_SBTOR5_PRE_TBTT0_x_INT_EN_SHFT         31
#define BN0_WF_LPON_TOP_SBTOR5_TBTT0_5_INT_EN_ADDR             BN0_WF_LPON_TOP_SBTOR5_ADDR
#define BN0_WF_LPON_TOP_SBTOR5_TBTT0_5_INT_EN_MASK             0x40000000                // TBTT0_5_INT_EN[30]
#define BN0_WF_LPON_TOP_SBTOR5_TBTT0_5_INT_EN_SHFT             30
#define BN0_WF_LPON_TOP_SBTOR5_SUB_BSSID0_TIME_OFFSET_5_ADDR   BN0_WF_LPON_TOP_SBTOR5_ADDR
#define BN0_WF_LPON_TOP_SBTOR5_SUB_BSSID0_TIME_OFFSET_5_MASK   0x000FFFFF                // SUB_BSSID0_TIME_OFFSET_5[19..0]
#define BN0_WF_LPON_TOP_SBTOR5_SUB_BSSID0_TIME_OFFSET_5_SHFT   0

/* =====================================================================================

  ---SBTOR6 (0x820EB000 + 0x050)---

    SUB_BSSID0_TIME_OFFSET_6[19..0] - (RW) Same as SUB BSSID time offset Value0 which includes n*(SIFS+ T6BcnTime) for TSF0, (n=6)
    RESERVED20[29..20]           - (RO) Reserved bits
    TBTT0_6_INT_EN[30]           - (RW) Enables TBTT0_6 INT
    PRE_TBTT0_x_INT_EN[31]       - (RW) Enables PRE_TBTT0_x INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOR6_PRE_TBTT0_x_INT_EN_ADDR         BN0_WF_LPON_TOP_SBTOR6_ADDR
#define BN0_WF_LPON_TOP_SBTOR6_PRE_TBTT0_x_INT_EN_MASK         0x80000000                // PRE_TBTT0_x_INT_EN[31]
#define BN0_WF_LPON_TOP_SBTOR6_PRE_TBTT0_x_INT_EN_SHFT         31
#define BN0_WF_LPON_TOP_SBTOR6_TBTT0_6_INT_EN_ADDR             BN0_WF_LPON_TOP_SBTOR6_ADDR
#define BN0_WF_LPON_TOP_SBTOR6_TBTT0_6_INT_EN_MASK             0x40000000                // TBTT0_6_INT_EN[30]
#define BN0_WF_LPON_TOP_SBTOR6_TBTT0_6_INT_EN_SHFT             30
#define BN0_WF_LPON_TOP_SBTOR6_SUB_BSSID0_TIME_OFFSET_6_ADDR   BN0_WF_LPON_TOP_SBTOR6_ADDR
#define BN0_WF_LPON_TOP_SBTOR6_SUB_BSSID0_TIME_OFFSET_6_MASK   0x000FFFFF                // SUB_BSSID0_TIME_OFFSET_6[19..0]
#define BN0_WF_LPON_TOP_SBTOR6_SUB_BSSID0_TIME_OFFSET_6_SHFT   0

/* =====================================================================================

  ---SBTOR7 (0x820EB000 + 0x054)---

    SUB_BSSID0_TIME_OFFSET_7[19..0] - (RW) Same as SUB BSSID time offset Value0 which includes n*(SIFS+ T7BcnTime) for TSF0, (n=7)
    RESERVED20[29..20]           - (RO) Reserved bits
    TBTT0_7_INT_EN[30]           - (RW) Enables TBTT0_7 INT
    PRE_TBTT0_x_INT_EN[31]       - (RW) Enables PRE_TBTT0_x INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOR7_PRE_TBTT0_x_INT_EN_ADDR         BN0_WF_LPON_TOP_SBTOR7_ADDR
#define BN0_WF_LPON_TOP_SBTOR7_PRE_TBTT0_x_INT_EN_MASK         0x80000000                // PRE_TBTT0_x_INT_EN[31]
#define BN0_WF_LPON_TOP_SBTOR7_PRE_TBTT0_x_INT_EN_SHFT         31
#define BN0_WF_LPON_TOP_SBTOR7_TBTT0_7_INT_EN_ADDR             BN0_WF_LPON_TOP_SBTOR7_ADDR
#define BN0_WF_LPON_TOP_SBTOR7_TBTT0_7_INT_EN_MASK             0x40000000                // TBTT0_7_INT_EN[30]
#define BN0_WF_LPON_TOP_SBTOR7_TBTT0_7_INT_EN_SHFT             30
#define BN0_WF_LPON_TOP_SBTOR7_SUB_BSSID0_TIME_OFFSET_7_ADDR   BN0_WF_LPON_TOP_SBTOR7_ADDR
#define BN0_WF_LPON_TOP_SBTOR7_SUB_BSSID0_TIME_OFFSET_7_MASK   0x000FFFFF                // SUB_BSSID0_TIME_OFFSET_7[19..0]
#define BN0_WF_LPON_TOP_SBTOR7_SUB_BSSID0_TIME_OFFSET_7_SHFT   0

/* =====================================================================================

  ---SBTOR8 (0x820EB000 + 0x058)---

    SUB_BSSID0_TIME_OFFSET_8[19..0] - (RW) Same as SUB BSSID time offset Value0 which includes n*(SIFS+ T8BcnTime) for TSF0, (n=8)
    RESERVED20[29..20]           - (RO) Reserved bits
    TBTT0_8_INT_EN[30]           - (RW) Enables TBTT0_8 INT
    PRE_TBTT0_x_INT_EN[31]       - (RW) Enables PRE_TBTT0_x INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOR8_PRE_TBTT0_x_INT_EN_ADDR         BN0_WF_LPON_TOP_SBTOR8_ADDR
#define BN0_WF_LPON_TOP_SBTOR8_PRE_TBTT0_x_INT_EN_MASK         0x80000000                // PRE_TBTT0_x_INT_EN[31]
#define BN0_WF_LPON_TOP_SBTOR8_PRE_TBTT0_x_INT_EN_SHFT         31
#define BN0_WF_LPON_TOP_SBTOR8_TBTT0_8_INT_EN_ADDR             BN0_WF_LPON_TOP_SBTOR8_ADDR
#define BN0_WF_LPON_TOP_SBTOR8_TBTT0_8_INT_EN_MASK             0x40000000                // TBTT0_8_INT_EN[30]
#define BN0_WF_LPON_TOP_SBTOR8_TBTT0_8_INT_EN_SHFT             30
#define BN0_WF_LPON_TOP_SBTOR8_SUB_BSSID0_TIME_OFFSET_8_ADDR   BN0_WF_LPON_TOP_SBTOR8_ADDR
#define BN0_WF_LPON_TOP_SBTOR8_SUB_BSSID0_TIME_OFFSET_8_MASK   0x000FFFFF                // SUB_BSSID0_TIME_OFFSET_8[19..0]
#define BN0_WF_LPON_TOP_SBTOR8_SUB_BSSID0_TIME_OFFSET_8_SHFT   0

/* =====================================================================================

  ---SBTOR9 (0x820EB000 + 0x05c)---

    SUB_BSSID0_TIME_OFFSET_9[19..0] - (RW) Same as SUB BSSID time offset Value0 which includes n*(SIFS+ T9BcnTime) for TSF0, (n=9)
    RESERVED20[29..20]           - (RO) Reserved bits
    TBTT0_9_INT_EN[30]           - (RW) Enables TBTT0_9 INT
    PRE_TBTT0_x_INT_EN[31]       - (RW) Enables PRE_TBTT0_x INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOR9_PRE_TBTT0_x_INT_EN_ADDR         BN0_WF_LPON_TOP_SBTOR9_ADDR
#define BN0_WF_LPON_TOP_SBTOR9_PRE_TBTT0_x_INT_EN_MASK         0x80000000                // PRE_TBTT0_x_INT_EN[31]
#define BN0_WF_LPON_TOP_SBTOR9_PRE_TBTT0_x_INT_EN_SHFT         31
#define BN0_WF_LPON_TOP_SBTOR9_TBTT0_9_INT_EN_ADDR             BN0_WF_LPON_TOP_SBTOR9_ADDR
#define BN0_WF_LPON_TOP_SBTOR9_TBTT0_9_INT_EN_MASK             0x40000000                // TBTT0_9_INT_EN[30]
#define BN0_WF_LPON_TOP_SBTOR9_TBTT0_9_INT_EN_SHFT             30
#define BN0_WF_LPON_TOP_SBTOR9_SUB_BSSID0_TIME_OFFSET_9_ADDR   BN0_WF_LPON_TOP_SBTOR9_ADDR
#define BN0_WF_LPON_TOP_SBTOR9_SUB_BSSID0_TIME_OFFSET_9_MASK   0x000FFFFF                // SUB_BSSID0_TIME_OFFSET_9[19..0]
#define BN0_WF_LPON_TOP_SBTOR9_SUB_BSSID0_TIME_OFFSET_9_SHFT   0

/* =====================================================================================

  ---SBTOR10 (0x820EB000 + 0x060)---

    SUB_BSSID0_TIME_OFFSET_10[19..0] - (RW) Same as SUB BSSID time offset Value0 which includes n*(SIFS+ T10BcnTime) for TSF0, (n=10)
    RESERVED20[29..20]           - (RO) Reserved bits
    TBTT0_10_INT_EN[30]          - (RW) Enables TBTT0_10 INT
    PRE_TBTT0_x_INT_EN[31]       - (RW) Enables PRE_TBTT0_x INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOR10_PRE_TBTT0_x_INT_EN_ADDR        BN0_WF_LPON_TOP_SBTOR10_ADDR
#define BN0_WF_LPON_TOP_SBTOR10_PRE_TBTT0_x_INT_EN_MASK        0x80000000                // PRE_TBTT0_x_INT_EN[31]
#define BN0_WF_LPON_TOP_SBTOR10_PRE_TBTT0_x_INT_EN_SHFT        31
#define BN0_WF_LPON_TOP_SBTOR10_TBTT0_10_INT_EN_ADDR           BN0_WF_LPON_TOP_SBTOR10_ADDR
#define BN0_WF_LPON_TOP_SBTOR10_TBTT0_10_INT_EN_MASK           0x40000000                // TBTT0_10_INT_EN[30]
#define BN0_WF_LPON_TOP_SBTOR10_TBTT0_10_INT_EN_SHFT           30
#define BN0_WF_LPON_TOP_SBTOR10_SUB_BSSID0_TIME_OFFSET_10_ADDR BN0_WF_LPON_TOP_SBTOR10_ADDR
#define BN0_WF_LPON_TOP_SBTOR10_SUB_BSSID0_TIME_OFFSET_10_MASK 0x000FFFFF                // SUB_BSSID0_TIME_OFFSET_10[19..0]
#define BN0_WF_LPON_TOP_SBTOR10_SUB_BSSID0_TIME_OFFSET_10_SHFT 0

/* =====================================================================================

  ---SBTOR11 (0x820EB000 + 0x064)---

    SUB_BSSID0_TIME_OFFSET_11[19..0] - (RW) Same as SUB BSSID time offset Value0 which includes n*(SIFS+ T11BcnTime) for TSF0, (n=11)
    RESERVED20[29..20]           - (RO) Reserved bits
    TBTT0_11_INT_EN[30]          - (RW) Enables TBTT0_11 INT
    PRE_TBTT0_x_INT_EN[31]       - (RW) Enables PRE_TBTT0_x INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOR11_PRE_TBTT0_x_INT_EN_ADDR        BN0_WF_LPON_TOP_SBTOR11_ADDR
#define BN0_WF_LPON_TOP_SBTOR11_PRE_TBTT0_x_INT_EN_MASK        0x80000000                // PRE_TBTT0_x_INT_EN[31]
#define BN0_WF_LPON_TOP_SBTOR11_PRE_TBTT0_x_INT_EN_SHFT        31
#define BN0_WF_LPON_TOP_SBTOR11_TBTT0_11_INT_EN_ADDR           BN0_WF_LPON_TOP_SBTOR11_ADDR
#define BN0_WF_LPON_TOP_SBTOR11_TBTT0_11_INT_EN_MASK           0x40000000                // TBTT0_11_INT_EN[30]
#define BN0_WF_LPON_TOP_SBTOR11_TBTT0_11_INT_EN_SHFT           30
#define BN0_WF_LPON_TOP_SBTOR11_SUB_BSSID0_TIME_OFFSET_11_ADDR BN0_WF_LPON_TOP_SBTOR11_ADDR
#define BN0_WF_LPON_TOP_SBTOR11_SUB_BSSID0_TIME_OFFSET_11_MASK 0x000FFFFF                // SUB_BSSID0_TIME_OFFSET_11[19..0]
#define BN0_WF_LPON_TOP_SBTOR11_SUB_BSSID0_TIME_OFFSET_11_SHFT 0

/* =====================================================================================

  ---SBTOR12 (0x820EB000 + 0x068)---

    SUB_BSSID0_TIME_OFFSET_12[19..0] - (RW) Same as SUB BSSID time offset Value0 which includes n*(SIFS+ T12BcnTime) for TSF0, (n=12)
    RESERVED20[29..20]           - (RO) Reserved bits
    TBTT0_12_INT_EN[30]          - (RW) Enables TBTT0_12 INT
    PRE_TBTT0_x_INT_EN[31]       - (RW) Enables PRE_TBTT0_x INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOR12_PRE_TBTT0_x_INT_EN_ADDR        BN0_WF_LPON_TOP_SBTOR12_ADDR
#define BN0_WF_LPON_TOP_SBTOR12_PRE_TBTT0_x_INT_EN_MASK        0x80000000                // PRE_TBTT0_x_INT_EN[31]
#define BN0_WF_LPON_TOP_SBTOR12_PRE_TBTT0_x_INT_EN_SHFT        31
#define BN0_WF_LPON_TOP_SBTOR12_TBTT0_12_INT_EN_ADDR           BN0_WF_LPON_TOP_SBTOR12_ADDR
#define BN0_WF_LPON_TOP_SBTOR12_TBTT0_12_INT_EN_MASK           0x40000000                // TBTT0_12_INT_EN[30]
#define BN0_WF_LPON_TOP_SBTOR12_TBTT0_12_INT_EN_SHFT           30
#define BN0_WF_LPON_TOP_SBTOR12_SUB_BSSID0_TIME_OFFSET_12_ADDR BN0_WF_LPON_TOP_SBTOR12_ADDR
#define BN0_WF_LPON_TOP_SBTOR12_SUB_BSSID0_TIME_OFFSET_12_MASK 0x000FFFFF                // SUB_BSSID0_TIME_OFFSET_12[19..0]
#define BN0_WF_LPON_TOP_SBTOR12_SUB_BSSID0_TIME_OFFSET_12_SHFT 0

/* =====================================================================================

  ---SBTOR13 (0x820EB000 + 0x06c)---

    SUB_BSSID0_TIME_OFFSET_13[19..0] - (RW) Same as SUB BSSID time offset Value0 which includes n*(SIFS+ T13BcnTime) for TSF0, (n=13)
    RESERVED20[29..20]           - (RO) Reserved bits
    TBTT0_13_INT_EN[30]          - (RW) Enables TBTT0_13 INT
    PRE_TBTT0_x_INT_EN[31]       - (RW) Enables PRE_TBTT0_x INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOR13_PRE_TBTT0_x_INT_EN_ADDR        BN0_WF_LPON_TOP_SBTOR13_ADDR
#define BN0_WF_LPON_TOP_SBTOR13_PRE_TBTT0_x_INT_EN_MASK        0x80000000                // PRE_TBTT0_x_INT_EN[31]
#define BN0_WF_LPON_TOP_SBTOR13_PRE_TBTT0_x_INT_EN_SHFT        31
#define BN0_WF_LPON_TOP_SBTOR13_TBTT0_13_INT_EN_ADDR           BN0_WF_LPON_TOP_SBTOR13_ADDR
#define BN0_WF_LPON_TOP_SBTOR13_TBTT0_13_INT_EN_MASK           0x40000000                // TBTT0_13_INT_EN[30]
#define BN0_WF_LPON_TOP_SBTOR13_TBTT0_13_INT_EN_SHFT           30
#define BN0_WF_LPON_TOP_SBTOR13_SUB_BSSID0_TIME_OFFSET_13_ADDR BN0_WF_LPON_TOP_SBTOR13_ADDR
#define BN0_WF_LPON_TOP_SBTOR13_SUB_BSSID0_TIME_OFFSET_13_MASK 0x000FFFFF                // SUB_BSSID0_TIME_OFFSET_13[19..0]
#define BN0_WF_LPON_TOP_SBTOR13_SUB_BSSID0_TIME_OFFSET_13_SHFT 0

/* =====================================================================================

  ---SBTOR14 (0x820EB000 + 0x070)---

    SUB_BSSID0_TIME_OFFSET_14[19..0] - (RW) Same as SUB BSSID time offset Value0 which includes n*(SIFS+ T14BcnTime) for TSF0, (n=14)
    RESERVED20[29..20]           - (RO) Reserved bits
    TBTT0_14_INT_EN[30]          - (RW) Enables TBTT0_14 INT
    PRE_TBTT0_x_INT_EN[31]       - (RW) Enables PRE_TBTT0_x INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOR14_PRE_TBTT0_x_INT_EN_ADDR        BN0_WF_LPON_TOP_SBTOR14_ADDR
#define BN0_WF_LPON_TOP_SBTOR14_PRE_TBTT0_x_INT_EN_MASK        0x80000000                // PRE_TBTT0_x_INT_EN[31]
#define BN0_WF_LPON_TOP_SBTOR14_PRE_TBTT0_x_INT_EN_SHFT        31
#define BN0_WF_LPON_TOP_SBTOR14_TBTT0_14_INT_EN_ADDR           BN0_WF_LPON_TOP_SBTOR14_ADDR
#define BN0_WF_LPON_TOP_SBTOR14_TBTT0_14_INT_EN_MASK           0x40000000                // TBTT0_14_INT_EN[30]
#define BN0_WF_LPON_TOP_SBTOR14_TBTT0_14_INT_EN_SHFT           30
#define BN0_WF_LPON_TOP_SBTOR14_SUB_BSSID0_TIME_OFFSET_14_ADDR BN0_WF_LPON_TOP_SBTOR14_ADDR
#define BN0_WF_LPON_TOP_SBTOR14_SUB_BSSID0_TIME_OFFSET_14_MASK 0x000FFFFF                // SUB_BSSID0_TIME_OFFSET_14[19..0]
#define BN0_WF_LPON_TOP_SBTOR14_SUB_BSSID0_TIME_OFFSET_14_SHFT 0

/* =====================================================================================

  ---SBTOR15 (0x820EB000 + 0x074)---

    SUB_BSSID0_TIME_OFFSET_15[19..0] - (RW) Same as SUB BSSID time offset Value0 which includes n*(SIFS+ T15BcnTime) for TSF0, (n=15)
    RESERVED20[29..20]           - (RO) Reserved bits
    TBTT0_15_INT_EN[30]          - (RW) Enables TBTT0_15 INT
    PRE_TBTT0_x_INT_EN[31]       - (RW) Enables PRE_TBTT0_x INT

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOR15_PRE_TBTT0_x_INT_EN_ADDR        BN0_WF_LPON_TOP_SBTOR15_ADDR
#define BN0_WF_LPON_TOP_SBTOR15_PRE_TBTT0_x_INT_EN_MASK        0x80000000                // PRE_TBTT0_x_INT_EN[31]
#define BN0_WF_LPON_TOP_SBTOR15_PRE_TBTT0_x_INT_EN_SHFT        31
#define BN0_WF_LPON_TOP_SBTOR15_TBTT0_15_INT_EN_ADDR           BN0_WF_LPON_TOP_SBTOR15_ADDR
#define BN0_WF_LPON_TOP_SBTOR15_TBTT0_15_INT_EN_MASK           0x40000000                // TBTT0_15_INT_EN[30]
#define BN0_WF_LPON_TOP_SBTOR15_TBTT0_15_INT_EN_SHFT           30
#define BN0_WF_LPON_TOP_SBTOR15_SUB_BSSID0_TIME_OFFSET_15_ADDR BN0_WF_LPON_TOP_SBTOR15_ADDR
#define BN0_WF_LPON_TOP_SBTOR15_SUB_BSSID0_TIME_OFFSET_15_MASK 0x000FFFFF                // SUB_BSSID0_TIME_OFFSET_15[19..0]
#define BN0_WF_LPON_TOP_SBTOR15_SUB_BSSID0_TIME_OFFSET_15_SHFT 0

/* =====================================================================================

  ---SBTOCR (0x820EB000 + 0x078)---

    LP_CR_MBSS_TOUT_CNT[19..0]   - (RW) HW local MBSS timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED20[31..20]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SBTOCR_LP_CR_MBSS_TOUT_CNT_ADDR        BN0_WF_LPON_TOP_SBTOCR_ADDR
#define BN0_WF_LPON_TOP_SBTOCR_LP_CR_MBSS_TOUT_CNT_MASK        0x000FFFFF                // LP_CR_MBSS_TOUT_CNT[19..0]
#define BN0_WF_LPON_TOP_SBTOCR_LP_CR_MBSS_TOUT_CNT_SHFT        0

/* =====================================================================================

  ---TSELR (0x820EB000 + 0x07c)---

    MBSSID_TSF_ENCODE[5..0]      - (RW) MBSSID TSF encode to TMAC and RMAC
                                     6'h00: BSSID0 TSF
                                     6'h01: BSSID1 TSF
                                     6'h02: BSSID2 TSF
                                     6'h03: BSSID3 TSF
                                     6'h11~1f: BSSID0_1~BSSID0_15 TSF
    RESERVED6[31..6]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TSELR_MBSSID_TSF_ENCODE_ADDR           BN0_WF_LPON_TOP_TSELR_ADDR
#define BN0_WF_LPON_TOP_TSELR_MBSSID_TSF_ENCODE_MASK           0x0000003F                // MBSSID_TSF_ENCODE[5..0]
#define BN0_WF_LPON_TOP_TSELR_MBSSID_TSF_ENCODE_SHFT           0

/* =====================================================================================

  ---UTTR0 (0x820EB000 + 0x080)---

    UPDATEDTSFTIMER_31_00[31..0] - (RW) Updated TSF timer turning value bit31~0
                                     This field may be used with different meaning controlled by TTAR. TSF_TIMER_SW_MODE.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_UTTR0_UPDATEDTSFTIMER_31_00_ADDR       BN0_WF_LPON_TOP_UTTR0_ADDR
#define BN0_WF_LPON_TOP_UTTR0_UPDATEDTSFTIMER_31_00_MASK       0xFFFFFFFF                // UPDATEDTSFTIMER_31_00[31..0]
#define BN0_WF_LPON_TOP_UTTR0_UPDATEDTSFTIMER_31_00_SHFT       0

/* =====================================================================================

  ---UTTR1 (0x820EB000 + 0x084)---

    UPDATEDTSFTIMER_63_32[31..0] - (RW) Updated TSF timer turning value bit63~32
                                     This field may be used with different meaning controlled by TTAR. TSF_TIMER_SW_MODE.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_UTTR1_UPDATEDTSFTIMER_63_32_ADDR       BN0_WF_LPON_TOP_UTTR1_ADDR
#define BN0_WF_LPON_TOP_UTTR1_UPDATEDTSFTIMER_63_32_MASK       0xFFFFFFFF                // UPDATEDTSFTIMER_63_32[31..0]
#define BN0_WF_LPON_TOP_UTTR1_UPDATEDTSFTIMER_63_32_SHFT       0

/* =====================================================================================

  ---LTTR0 (0x820EB000 + 0x088)---

    LP_TSF0_CNT_L[31..0]         - (RU) HW local TSF0 counter bit [31:0]
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LTTR0_LP_TSF0_CNT_L_ADDR               BN0_WF_LPON_TOP_LTTR0_ADDR
#define BN0_WF_LPON_TOP_LTTR0_LP_TSF0_CNT_L_MASK               0xFFFFFFFF                // LP_TSF0_CNT_L[31..0]
#define BN0_WF_LPON_TOP_LTTR0_LP_TSF0_CNT_L_SHFT               0

/* =====================================================================================

  ---LTTR1 (0x820EB000 + 0x08c)---

    LP_TSF0_CNT_H[31..0]         - (RU) HW local TSF0 counter bit [63:32]
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LTTR1_LP_TSF0_CNT_H_ADDR               BN0_WF_LPON_TOP_LTTR1_ADDR
#define BN0_WF_LPON_TOP_LTTR1_LP_TSF0_CNT_H_MASK               0xFFFFFFFF                // LP_TSF0_CNT_H[31..0]
#define BN0_WF_LPON_TOP_LTTR1_LP_TSF0_CNT_H_SHFT               0

/* =====================================================================================

  ---LTTR2 (0x820EB000 + 0x090)---

    LP_TSF1_CNT_L[31..0]         - (RU) HW local TSF1 counter bit [31:0]
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LTTR2_LP_TSF1_CNT_L_ADDR               BN0_WF_LPON_TOP_LTTR2_ADDR
#define BN0_WF_LPON_TOP_LTTR2_LP_TSF1_CNT_L_MASK               0xFFFFFFFF                // LP_TSF1_CNT_L[31..0]
#define BN0_WF_LPON_TOP_LTTR2_LP_TSF1_CNT_L_SHFT               0

/* =====================================================================================

  ---LTTR3 (0x820EB000 + 0x094)---

    LP_TSF1_CNT_H[31..0]         - (RU) HW local TSF1 counter bit [63:32]
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LTTR3_LP_TSF1_CNT_H_ADDR               BN0_WF_LPON_TOP_LTTR3_ADDR
#define BN0_WF_LPON_TOP_LTTR3_LP_TSF1_CNT_H_MASK               0xFFFFFFFF                // LP_TSF1_CNT_H[31..0]
#define BN0_WF_LPON_TOP_LTTR3_LP_TSF1_CNT_H_SHFT               0

/* =====================================================================================

  ---LTTR4 (0x820EB000 + 0x098)---

    LP_TSF2_CNT_L[31..0]         - (RU) HW local TSF2 counter bit [31:0]
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LTTR4_LP_TSF2_CNT_L_ADDR               BN0_WF_LPON_TOP_LTTR4_ADDR
#define BN0_WF_LPON_TOP_LTTR4_LP_TSF2_CNT_L_MASK               0xFFFFFFFF                // LP_TSF2_CNT_L[31..0]
#define BN0_WF_LPON_TOP_LTTR4_LP_TSF2_CNT_L_SHFT               0

/* =====================================================================================

  ---LTTR5 (0x820EB000 + 0x09c)---

    LP_TSF2_CNT_H[31..0]         - (RU) HW local TSF2 counter bit [63:32]
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LTTR5_LP_TSF2_CNT_H_ADDR               BN0_WF_LPON_TOP_LTTR5_ADDR
#define BN0_WF_LPON_TOP_LTTR5_LP_TSF2_CNT_H_MASK               0xFFFFFFFF                // LP_TSF2_CNT_H[31..0]
#define BN0_WF_LPON_TOP_LTTR5_LP_TSF2_CNT_H_SHFT               0

/* =====================================================================================

  ---LTTR6 (0x820EB000 + 0x0a0)---

    LP_TSF3_CNT_L[31..0]         - (RU) HW local TSF3 counter bit [31:0]
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LTTR6_LP_TSF3_CNT_L_ADDR               BN0_WF_LPON_TOP_LTTR6_ADDR
#define BN0_WF_LPON_TOP_LTTR6_LP_TSF3_CNT_L_MASK               0xFFFFFFFF                // LP_TSF3_CNT_L[31..0]
#define BN0_WF_LPON_TOP_LTTR6_LP_TSF3_CNT_L_SHFT               0

/* =====================================================================================

  ---LTTR7 (0x820EB000 + 0x0a4)---

    LP_TSF3_CNT_H[31..0]         - (RU) HW local TSF3 counter bit [63:32]
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LTTR7_LP_TSF3_CNT_H_ADDR               BN0_WF_LPON_TOP_LTTR7_ADDR
#define BN0_WF_LPON_TOP_LTTR7_LP_TSF3_CNT_H_MASK               0xFFFFFFFF                // LP_TSF3_CNT_H[31..0]
#define BN0_WF_LPON_TOP_LTTR7_LP_TSF3_CNT_H_SHFT               0

/* =====================================================================================

  ---T0CR (0x820EB000 + 0x0a8)---

    TSF0_TIMER_SW_MODE[1..0]     - (RW) Configures TSF update control of LTT0 (Local TSF Timer 0) by SW
                                     Write:
                                     2'h0: No meaning
                                     2'h1: TSFTIMERVALUECHANGE 
                                     It updates its corresponding local TSF timer value through UTTR0 by loading it to the local TSF timer directly. 
                                     2'h2: TSFTIMERVALUEADJUST
                                     It updates its corresponding local TSF timer value through UTTR0 by using it as a TSF offset and will be added with the current local TSF timer. 
                                     2'h3: TSFTIMERVALUEREAD
                                     HW will latch the current TSF 0 and update it to UTTR0/1.
                                     Read: Meaningless
    TSF0_TIMER_HW_MODE[3..2]     - (RW) Configures TSF update control of LTT0 (Local TSF Timer 0) by HW
                                     2'h0: HW will update TSF by timer tick and will update it after beacon or probe response frame from the same BSS received in STA mode-like rule: always update TSF after beacon received or probe response frame.
                                     2'h1: Hardware will not update TSF by the received beacon or probe response and will only be updated by timer tick (used whenever SW mode is used to update TSF).
                                     2'h2: HW will update TSF by the received beacon or probe response and will not update it by timer tick (purely for emulation purpose).
                                     2'h3: HW will update TSF by timer tick and will update it after beacon or probe response frame from the same BSS received in Ad hoc mode-like rule: update TSF if TSF field in received beacon or probe response frame is greater than local TSF.
    TSF0_SET_MASK[4]             - (RW) This field will be used to fix under dual  AP tx beacon issue
                                     0:Receiving the beacon issued by another AP with the same MAC address(original function)
                                     1:Ignore the beacon from another AP with the same MAC address
    RESERVED5[15..5]             - (RO) Reserved bits
    TSF0_MAX_DRIFT_WINDOW[23..16] - (RW) This field defines the drifting window (unit: TU) to generate WISR.TSF0_drift or not. When the TSF value difference between the received BSS beacon frame outside the window and local TSF value is bigger than this setting, WISR0.TSF0_drift will be asserted. See the previous figure for the illustration of this idea.
                                     Write:
                                     0: Disable TSF drift detection; will not generate interrupt by TSF update.
    TSF0_MIN_DRIFT_WINDOW[31..24] - (RW) This field defines the drifting window (unit: TU) to generate WISR.TSF0_drift or not. When the TSF value difference between the received BSS beacon frame outside the window and local TSF value is bigger than this setting, WISR0.TSF0_drift will be asserted. See the previous figure for the illustration of this idea.
                                     Write:
                                     0: Disable TSF drift detection; will not generate interrupt by TSF update.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T0CR_TSF0_MIN_DRIFT_WINDOW_ADDR        BN0_WF_LPON_TOP_T0CR_ADDR
#define BN0_WF_LPON_TOP_T0CR_TSF0_MIN_DRIFT_WINDOW_MASK        0xFF000000                // TSF0_MIN_DRIFT_WINDOW[31..24]
#define BN0_WF_LPON_TOP_T0CR_TSF0_MIN_DRIFT_WINDOW_SHFT        24
#define BN0_WF_LPON_TOP_T0CR_TSF0_MAX_DRIFT_WINDOW_ADDR        BN0_WF_LPON_TOP_T0CR_ADDR
#define BN0_WF_LPON_TOP_T0CR_TSF0_MAX_DRIFT_WINDOW_MASK        0x00FF0000                // TSF0_MAX_DRIFT_WINDOW[23..16]
#define BN0_WF_LPON_TOP_T0CR_TSF0_MAX_DRIFT_WINDOW_SHFT        16
#define BN0_WF_LPON_TOP_T0CR_TSF0_SET_MASK_ADDR                BN0_WF_LPON_TOP_T0CR_ADDR
#define BN0_WF_LPON_TOP_T0CR_TSF0_SET_MASK_MASK                0x00000010                // TSF0_SET_MASK[4]
#define BN0_WF_LPON_TOP_T0CR_TSF0_SET_MASK_SHFT                4
#define BN0_WF_LPON_TOP_T0CR_TSF0_TIMER_HW_MODE_ADDR           BN0_WF_LPON_TOP_T0CR_ADDR
#define BN0_WF_LPON_TOP_T0CR_TSF0_TIMER_HW_MODE_MASK           0x0000000C                // TSF0_TIMER_HW_MODE[3..2]
#define BN0_WF_LPON_TOP_T0CR_TSF0_TIMER_HW_MODE_SHFT           2
#define BN0_WF_LPON_TOP_T0CR_TSF0_TIMER_SW_MODE_ADDR           BN0_WF_LPON_TOP_T0CR_ADDR
#define BN0_WF_LPON_TOP_T0CR_TSF0_TIMER_SW_MODE_MASK           0x00000003                // TSF0_TIMER_SW_MODE[1..0]
#define BN0_WF_LPON_TOP_T0CR_TSF0_TIMER_SW_MODE_SHFT           0

/* =====================================================================================

  ---T1CR (0x820EB000 + 0x0ac)---

    TSF1_TIMER_SW_MODE[1..0]     - (RW) Configures TSF update control of LTT1 (Local TSF Timer 1) by SW
                                     Write:
                                     2'h0: No meaning
                                     2'h1: TSFTIMERVALUECHANGE 
                                     It updates its corresponding local TSF timer value through UTTR0 by loading it to the local TSF timer directly. 
                                     2'h2: TSFTIMERVALUEADJUST
                                     It updates its corresponding local TSF timer value through UTTR0 by using it as a TSF offset and will be added with the current local TSF timer. 
                                     2'h3: TSFTIMERVALUEREAD
                                     HW will latch the current TSF 1 and update it to UTTR0/1.
                                     Read: Meaningless
    TSF1_TIMER_HW_MODE[3..2]     - (RW) Configures TSF update control of LTT1 (Local TSF Timer 1) by HW
                                     2'h0: HW will update TSF by timer tick and will update it after beacon or probe response frame from the same BSS received in STA mode-like rule: always update TSF after beacon received or probe response frame.
                                     2'h1: Hardware will not update TSF by the received beacon/probe response and will only be updated by timer tick (used whenever SW mode is used to update TSF).
                                     2'h2: HW will update TSF by the received beacon/probe response and will not update it by timer tick (purely for emulation purpose).
                                     2'h3: HW will update TSF by timer tick and will update it after beacon or probe response frame from the same BSS received in Ad hoc mode-like rule: update TSF if TSF field in received beacon or probe response frame is greater than local TSF.
    TSF1_SET_MASK[4]             - (RW) This field will be used to fix under dual  AP tx beacon issue
                                     0:Receiving the beacon issued by another AP with the same MAC address(original function)
                                     1:Ignore the beacon from another AP with the same MAC address
    RESERVED5[15..5]             - (RO) Reserved bits
    TSF1_MAX_DRIFT_WINDOW[23..16] - (RW) This field defines the drifting window (unit: TU) to generate WISR.TSF1_drift or not. When the TSF value difference between the received BSS beacon frame outside the window and local TSF value is bigger than this setting, WISR0.TSF1_drift will be asserted. See the previous figure for the illustration of this idea.
                                     Write:
                                     0: Disable TSF drift detection; will not generate interrupt by TSF update.
    TSF1_MIN_DRIFT_WINDOW[31..24] - (RW) This field defines the drifting window (unit: TU) to generate WISR.TSF1_drift or not. When the TSF value difference between the received BSS beacon frame outside the window and local TSF value is bigger than this setting, WISR0.TSF1_drift will be asserted. See the previous figure for the illustration of this idea.
                                     Write:
                                     0: Disable TSF drift detection; will not generate interrupt by TSF update.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T1CR_TSF1_MIN_DRIFT_WINDOW_ADDR        BN0_WF_LPON_TOP_T1CR_ADDR
#define BN0_WF_LPON_TOP_T1CR_TSF1_MIN_DRIFT_WINDOW_MASK        0xFF000000                // TSF1_MIN_DRIFT_WINDOW[31..24]
#define BN0_WF_LPON_TOP_T1CR_TSF1_MIN_DRIFT_WINDOW_SHFT        24
#define BN0_WF_LPON_TOP_T1CR_TSF1_MAX_DRIFT_WINDOW_ADDR        BN0_WF_LPON_TOP_T1CR_ADDR
#define BN0_WF_LPON_TOP_T1CR_TSF1_MAX_DRIFT_WINDOW_MASK        0x00FF0000                // TSF1_MAX_DRIFT_WINDOW[23..16]
#define BN0_WF_LPON_TOP_T1CR_TSF1_MAX_DRIFT_WINDOW_SHFT        16
#define BN0_WF_LPON_TOP_T1CR_TSF1_SET_MASK_ADDR                BN0_WF_LPON_TOP_T1CR_ADDR
#define BN0_WF_LPON_TOP_T1CR_TSF1_SET_MASK_MASK                0x00000010                // TSF1_SET_MASK[4]
#define BN0_WF_LPON_TOP_T1CR_TSF1_SET_MASK_SHFT                4
#define BN0_WF_LPON_TOP_T1CR_TSF1_TIMER_HW_MODE_ADDR           BN0_WF_LPON_TOP_T1CR_ADDR
#define BN0_WF_LPON_TOP_T1CR_TSF1_TIMER_HW_MODE_MASK           0x0000000C                // TSF1_TIMER_HW_MODE[3..2]
#define BN0_WF_LPON_TOP_T1CR_TSF1_TIMER_HW_MODE_SHFT           2
#define BN0_WF_LPON_TOP_T1CR_TSF1_TIMER_SW_MODE_ADDR           BN0_WF_LPON_TOP_T1CR_ADDR
#define BN0_WF_LPON_TOP_T1CR_TSF1_TIMER_SW_MODE_MASK           0x00000003                // TSF1_TIMER_SW_MODE[1..0]
#define BN0_WF_LPON_TOP_T1CR_TSF1_TIMER_SW_MODE_SHFT           0

/* =====================================================================================

  ---T2CR (0x820EB000 + 0x0b0)---

    TSF2_TIMER_SW_MODE[1..0]     - (RW) Configures TSF update control of LTT2 (Local TSF Timer 2) by SW.
                                     When write:
                                     2'h0: No meaning
                                     2'h1: TSFTIMERVALUECHANGE 
                                     It updates its corresponding local TSF timer value through UTTR0 by loading it to the local TSF timer directly. 
                                     2'h2: TSFTIMERVALUEADJUST
                                     It updates its corresponding local TSF timer value through UTTR0 by using it as a TSF offset and will be added with the current local TSF timer. 
                                     2'h3: TSFTIMERVALUEREAD
                                     HW will latch current TSF 2 and updated it to UTTR0/1.
                                     Read: Meaningless
    TSF2_TIMER_HW_MODE[3..2]     - (RW) Configures TSF update control of LTT2 (Local TSF Timer 2) by HW.
                                     2'h0: HW will update TSF by timer tick and will update it after beacon or probe response frame from the same BSS received in STA mode-like rule: always update TSF after beacon received or probe response frame.
                                     2'h1: Hardware will not update TSF by the received beacon/probe response and will only be updated by timer tick (used whenever SW mode is used to update TSF).
                                     2'h2: HW will update TSF by the received beacon/probe response and will not update it by timer tick (purely for emulation purpose).
                                     2'h3: HW will update TSF by timer tick and will update it after beacon or probe response frame from the same BSS received in Ad hoc mode-like rule: update TSF if TSF field in received beacon or probe response frame is greater than local TSF.
    TSF2_SET_MASK[4]             - (RW) This field will be used to fix under dual  AP tx beacon issue
                                     0:Receiving the beacon issued by another AP with the same MAC address(original function)
                                     1:Ignore the beacon from another AP with the same MAC address
    RESERVED5[15..5]             - (RO) Reserved bits
    TSF2_MAX_DRIFT_WINDOW[23..16] - (RW) This field defines the drifting window (unit: TU) to generate WISR.TSF2_drift or not. When the TSF value difference between the received BSS beacon frame outside the window and local TSF value is bigger than this setting, WISR0.TSF2_drift will be asserted. See the previous figure for the illustration of this idea.
                                     Write:
                                     0: Disable TSF drift detection; will not generate interrupt by TSF update
    TSF2_MIN_DRIFT_WINDOW[31..24] - (RW) This field defines the drifting window (unit: TU) to generate WISR.TSF2_drift or not. When the TSF value difference between the received BSS beacon frame outside the window and local TSF value is bigger than this setting, WISR0.TSF2_drift will be asserted. See the previous figure for the illustration of this idea.
                                     Write:
                                     0: Disable TSF drift detection; will not generate interrupt by TSF update

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T2CR_TSF2_MIN_DRIFT_WINDOW_ADDR        BN0_WF_LPON_TOP_T2CR_ADDR
#define BN0_WF_LPON_TOP_T2CR_TSF2_MIN_DRIFT_WINDOW_MASK        0xFF000000                // TSF2_MIN_DRIFT_WINDOW[31..24]
#define BN0_WF_LPON_TOP_T2CR_TSF2_MIN_DRIFT_WINDOW_SHFT        24
#define BN0_WF_LPON_TOP_T2CR_TSF2_MAX_DRIFT_WINDOW_ADDR        BN0_WF_LPON_TOP_T2CR_ADDR
#define BN0_WF_LPON_TOP_T2CR_TSF2_MAX_DRIFT_WINDOW_MASK        0x00FF0000                // TSF2_MAX_DRIFT_WINDOW[23..16]
#define BN0_WF_LPON_TOP_T2CR_TSF2_MAX_DRIFT_WINDOW_SHFT        16
#define BN0_WF_LPON_TOP_T2CR_TSF2_SET_MASK_ADDR                BN0_WF_LPON_TOP_T2CR_ADDR
#define BN0_WF_LPON_TOP_T2CR_TSF2_SET_MASK_MASK                0x00000010                // TSF2_SET_MASK[4]
#define BN0_WF_LPON_TOP_T2CR_TSF2_SET_MASK_SHFT                4
#define BN0_WF_LPON_TOP_T2CR_TSF2_TIMER_HW_MODE_ADDR           BN0_WF_LPON_TOP_T2CR_ADDR
#define BN0_WF_LPON_TOP_T2CR_TSF2_TIMER_HW_MODE_MASK           0x0000000C                // TSF2_TIMER_HW_MODE[3..2]
#define BN0_WF_LPON_TOP_T2CR_TSF2_TIMER_HW_MODE_SHFT           2
#define BN0_WF_LPON_TOP_T2CR_TSF2_TIMER_SW_MODE_ADDR           BN0_WF_LPON_TOP_T2CR_ADDR
#define BN0_WF_LPON_TOP_T2CR_TSF2_TIMER_SW_MODE_MASK           0x00000003                // TSF2_TIMER_SW_MODE[1..0]
#define BN0_WF_LPON_TOP_T2CR_TSF2_TIMER_SW_MODE_SHFT           0

/* =====================================================================================

  ---T3CR (0x820EB000 + 0x0b4)---

    TSF3_TIMER_SW_MODE[1..0]     - (RW) Configures TSF update control of LTT3 (Local TSF Timer 3) by SW.
                                     When write:
                                     2'h0: No meaning
                                     2'h1: TSFTIMERVALUECHANGE 
                                     It updates its corresponding local TSF timer value through UTTR0 by loading it to the local TSF timer directly. 
                                     2'h2: TSFTIMERVALUEADJUST
                                     It updates its corresponding local TSF timer value through UTTR0 by using it as a TSF offset and will be added with the current local TSF timer. 
                                     2'h3: TSFTIMERVALUEREAD
                                     HW will latch current TSF 3 and updated it to UTTR0/1.
                                     Read: Meaningless
    TSF3_TIMER_HW_MODE[3..2]     - (RW) Configures TSF update control of LTT3 (Local TSF Timer 3) by HW.
                                     2'h0: HW will update TSF by timer tick and will update it after beacon or probe response frame from the same BSS received in STA mode-like rule: always update TSF after beacon received or probe response frame.
                                     2'h1: Hardware will not update TSF by the received beacon/probe response and will only be updated by timer tick (used whenever SW mode is used to update TSF).
                                     2'h2: HW will update TSF by the received beacon/probe response and will not update it by timer tick (purely for emulation purpose).
                                     2'h3: HW will update TSF by timer tick and will update it after beacon or probe response frame from the same BSS received in Ad hoc mode-like rule: update TSF if TSF field in received beacon or probe response frame is greater than local TSF.
    TSF3_SET_MASK[4]             - (RW) This field will be used to fix under dual  AP tx beacon issue
                                     0:Receiving the beacon issued by another AP with the same MAC address(original function)
                                     1:Ignore the beacon from another AP with the same MAC address
    RESERVED5[15..5]             - (RO) Reserved bits
    TSF3_MAX_DRIFT_WINDOW[23..16] - (RW) This field defines the drifting window (unit: TU) to generate WISR.TSF3_drift or not. When the TSF value difference between the received BSS beacon frame outside the window and local TSF value is bigger than this setting, WISR0.TSF3_drift will be asserted. See the previous figure for the illustration of this idea.
                                     Write:
                                     0: Disable TSF drift detection; will not generate interrupt by TSF update
    TSF3_MIN_DRIFT_WINDOW[31..24] - (RW) This field defines the drifting window (unit: TU) to generate WISR.TSF3_drift or not. When the TSF value difference between the received BSS beacon frame outside the window and local TSF value is bigger than this setting, WISR0.TSF3_drift will be asserted. See the previous figure for the illustration of this idea.
                                     Write:
                                     0: Disable TSF drift detection; will not generate interrupt by TSF update

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T3CR_TSF3_MIN_DRIFT_WINDOW_ADDR        BN0_WF_LPON_TOP_T3CR_ADDR
#define BN0_WF_LPON_TOP_T3CR_TSF3_MIN_DRIFT_WINDOW_MASK        0xFF000000                // TSF3_MIN_DRIFT_WINDOW[31..24]
#define BN0_WF_LPON_TOP_T3CR_TSF3_MIN_DRIFT_WINDOW_SHFT        24
#define BN0_WF_LPON_TOP_T3CR_TSF3_MAX_DRIFT_WINDOW_ADDR        BN0_WF_LPON_TOP_T3CR_ADDR
#define BN0_WF_LPON_TOP_T3CR_TSF3_MAX_DRIFT_WINDOW_MASK        0x00FF0000                // TSF3_MAX_DRIFT_WINDOW[23..16]
#define BN0_WF_LPON_TOP_T3CR_TSF3_MAX_DRIFT_WINDOW_SHFT        16
#define BN0_WF_LPON_TOP_T3CR_TSF3_SET_MASK_ADDR                BN0_WF_LPON_TOP_T3CR_ADDR
#define BN0_WF_LPON_TOP_T3CR_TSF3_SET_MASK_MASK                0x00000010                // TSF3_SET_MASK[4]
#define BN0_WF_LPON_TOP_T3CR_TSF3_SET_MASK_SHFT                4
#define BN0_WF_LPON_TOP_T3CR_TSF3_TIMER_HW_MODE_ADDR           BN0_WF_LPON_TOP_T3CR_ADDR
#define BN0_WF_LPON_TOP_T3CR_TSF3_TIMER_HW_MODE_MASK           0x0000000C                // TSF3_TIMER_HW_MODE[3..2]
#define BN0_WF_LPON_TOP_T3CR_TSF3_TIMER_HW_MODE_SHFT           2
#define BN0_WF_LPON_TOP_T3CR_TSF3_TIMER_SW_MODE_ADDR           BN0_WF_LPON_TOP_T3CR_ADDR
#define BN0_WF_LPON_TOP_T3CR_TSF3_TIMER_SW_MODE_MASK           0x00000003                // TSF3_TIMER_SW_MODE[1..0]
#define BN0_WF_LPON_TOP_T3CR_TSF3_TIMER_SW_MODE_SHFT           0

/* =====================================================================================

  ---T0DVR (0x820EB000 + 0x0b8)---

    TSF0_DRIFT_TRUNC[22..0]      - (RW) Indicate TSF drift absolute truncated value (unit : us)
    TSF0_DRIFT_POLARITY[23]      - (RW) Indicate TSF drift polarity :
                                     1 : negative , update TSF is smaller than local TSF.
                                     0 : postive , update TSF is larger than local TSF.
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T0DVR_TSF0_DRIFT_POLARITY_ADDR         BN0_WF_LPON_TOP_T0DVR_ADDR
#define BN0_WF_LPON_TOP_T0DVR_TSF0_DRIFT_POLARITY_MASK         0x00800000                // TSF0_DRIFT_POLARITY[23]
#define BN0_WF_LPON_TOP_T0DVR_TSF0_DRIFT_POLARITY_SHFT         23
#define BN0_WF_LPON_TOP_T0DVR_TSF0_DRIFT_TRUNC_ADDR            BN0_WF_LPON_TOP_T0DVR_ADDR
#define BN0_WF_LPON_TOP_T0DVR_TSF0_DRIFT_TRUNC_MASK            0x007FFFFF                // TSF0_DRIFT_TRUNC[22..0]
#define BN0_WF_LPON_TOP_T0DVR_TSF0_DRIFT_TRUNC_SHFT            0

/* =====================================================================================

  ---T1DVR (0x820EB000 + 0x0bc)---

    TSF1_DRIFT_TRUNC[22..0]      - (RW) Indicate TSF drift absolute truncated value (unit : us)
    TSF1_DRIFT_POLARITY[23]      - (RW) Indicate TSF drift polarity :
                                     1 : negative , update TSF is smaller than local TSF.
                                     0 : postive , update TSF is larger than local TSF.
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T1DVR_TSF1_DRIFT_POLARITY_ADDR         BN0_WF_LPON_TOP_T1DVR_ADDR
#define BN0_WF_LPON_TOP_T1DVR_TSF1_DRIFT_POLARITY_MASK         0x00800000                // TSF1_DRIFT_POLARITY[23]
#define BN0_WF_LPON_TOP_T1DVR_TSF1_DRIFT_POLARITY_SHFT         23
#define BN0_WF_LPON_TOP_T1DVR_TSF1_DRIFT_TRUNC_ADDR            BN0_WF_LPON_TOP_T1DVR_ADDR
#define BN0_WF_LPON_TOP_T1DVR_TSF1_DRIFT_TRUNC_MASK            0x007FFFFF                // TSF1_DRIFT_TRUNC[22..0]
#define BN0_WF_LPON_TOP_T1DVR_TSF1_DRIFT_TRUNC_SHFT            0

/* =====================================================================================

  ---T2DVR (0x820EB000 + 0x0c0)---

    TSF2_DRIFT_TRUNC[22..0]      - (RW) Indicate TSF drift absolute truncated value (unit : us)
    TSF2_DRIFT_POLARITY[23]      - (RW) Indicate TSF drift polarity :
                                     1 : negative , update TSF is smaller than local TSF.
                                     0 : postive , update TSF is larger than local TSF.
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T2DVR_TSF2_DRIFT_POLARITY_ADDR         BN0_WF_LPON_TOP_T2DVR_ADDR
#define BN0_WF_LPON_TOP_T2DVR_TSF2_DRIFT_POLARITY_MASK         0x00800000                // TSF2_DRIFT_POLARITY[23]
#define BN0_WF_LPON_TOP_T2DVR_TSF2_DRIFT_POLARITY_SHFT         23
#define BN0_WF_LPON_TOP_T2DVR_TSF2_DRIFT_TRUNC_ADDR            BN0_WF_LPON_TOP_T2DVR_ADDR
#define BN0_WF_LPON_TOP_T2DVR_TSF2_DRIFT_TRUNC_MASK            0x007FFFFF                // TSF2_DRIFT_TRUNC[22..0]
#define BN0_WF_LPON_TOP_T2DVR_TSF2_DRIFT_TRUNC_SHFT            0

/* =====================================================================================

  ---T3DVR (0x820EB000 + 0x0c4)---

    TSF3_DRIFT_TRUNC[22..0]      - (RW) Indicate TSF drift absolute truncated value (unit : us)
    TSF3_DRIFT_POLARITY[23]      - (RW) Indicate TSF drift polarity :
                                     1 : negative , update TSF is smaller than local TSF.
                                     0 : postive , update TSF is larger than local TSF.
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T3DVR_TSF3_DRIFT_POLARITY_ADDR         BN0_WF_LPON_TOP_T3DVR_ADDR
#define BN0_WF_LPON_TOP_T3DVR_TSF3_DRIFT_POLARITY_MASK         0x00800000                // TSF3_DRIFT_POLARITY[23]
#define BN0_WF_LPON_TOP_T3DVR_TSF3_DRIFT_POLARITY_SHFT         23
#define BN0_WF_LPON_TOP_T3DVR_TSF3_DRIFT_TRUNC_ADDR            BN0_WF_LPON_TOP_T3DVR_ADDR
#define BN0_WF_LPON_TOP_T3DVR_TSF3_DRIFT_TRUNC_MASK            0x007FFFFF                // TSF3_DRIFT_TRUNC[22..0]
#define BN0_WF_LPON_TOP_T3DVR_TSF3_DRIFT_TRUNC_SHFT            0

/* =====================================================================================

  ---T0STR (0x820EB000 + 0x0c8)---

    NEXT_TBTT0_TIME[15..0]       - (RU) Indicates the value of the next TBTT timer which is enabled to be counted down when MPTCR0. PREDTIM_TRIG_EN.
                                     TBTT time is count in unit of TU compared to local TSF timer bit 25~10.
                                     Refer to TTPCR. TBTT_CAL_EN for how HW updates this value. SW is also able to set up the initial value, with TBTT time in unit of TU compared to TSF timer bit25~10.
                                     Read: Next TBTT time in unit of TU
    DTIM_COUNT0[23..16]          - (RU) Indicates the value of local DTIM0 count which is enabled to be counted down when MPTCR0. PREDTIM_TRIG_EN
                                     SW is also able to set up the initial value for DTIM0 count-down by writing to this field.
    RESERVED24[28..24]           - (RO) Reserved bits
    TBTT0_CAL_BUSY[29]           - (RU) Calculates TBTT0 BUSY
    UPDATE_NEXT_TBTT0[30]        - (WO) Write:
                                     0: Meaningless
                                     1: NEXT_TBTT0_TIME is valid and to be updated.
    UPDATE_DTIM_COUNT0[31]       - (WO) Write:
                                     0: Meaningless
                                     1: DTIM_COUNT0 is valid and to be updated.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T0STR_UPDATE_DTIM_COUNT0_ADDR          BN0_WF_LPON_TOP_T0STR_ADDR
#define BN0_WF_LPON_TOP_T0STR_UPDATE_DTIM_COUNT0_MASK          0x80000000                // UPDATE_DTIM_COUNT0[31]
#define BN0_WF_LPON_TOP_T0STR_UPDATE_DTIM_COUNT0_SHFT          31
#define BN0_WF_LPON_TOP_T0STR_UPDATE_NEXT_TBTT0_ADDR           BN0_WF_LPON_TOP_T0STR_ADDR
#define BN0_WF_LPON_TOP_T0STR_UPDATE_NEXT_TBTT0_MASK           0x40000000                // UPDATE_NEXT_TBTT0[30]
#define BN0_WF_LPON_TOP_T0STR_UPDATE_NEXT_TBTT0_SHFT           30
#define BN0_WF_LPON_TOP_T0STR_TBTT0_CAL_BUSY_ADDR              BN0_WF_LPON_TOP_T0STR_ADDR
#define BN0_WF_LPON_TOP_T0STR_TBTT0_CAL_BUSY_MASK              0x20000000                // TBTT0_CAL_BUSY[29]
#define BN0_WF_LPON_TOP_T0STR_TBTT0_CAL_BUSY_SHFT              29
#define BN0_WF_LPON_TOP_T0STR_DTIM_COUNT0_ADDR                 BN0_WF_LPON_TOP_T0STR_ADDR
#define BN0_WF_LPON_TOP_T0STR_DTIM_COUNT0_MASK                 0x00FF0000                // DTIM_COUNT0[23..16]
#define BN0_WF_LPON_TOP_T0STR_DTIM_COUNT0_SHFT                 16
#define BN0_WF_LPON_TOP_T0STR_NEXT_TBTT0_TIME_ADDR             BN0_WF_LPON_TOP_T0STR_ADDR
#define BN0_WF_LPON_TOP_T0STR_NEXT_TBTT0_TIME_MASK             0x0000FFFF                // NEXT_TBTT0_TIME[15..0]
#define BN0_WF_LPON_TOP_T0STR_NEXT_TBTT0_TIME_SHFT             0

/* =====================================================================================

  ---T1STR (0x820EB000 + 0x0cc)---

    NEXT_TBTT1_TIME[15..0]       - (RU) Indicates the value of the next TBTT timer which is enabled to be counted down when MPTCR1. PREDTIM_TRIG_EN
                                     TBTT time is count in unit of TU compared to local TSF timer bit 25~11.
                                     Refer to TTPCR. TBTT_CAL_EN for how HW updates this value. SW is also able to set up the initial value, with TBTT time in unit of TU compared to TSF timer bit25~11.
                                     Read: Next TBTT time in unit of TU
    DTIM_COUNT1[23..16]          - (RU) Indicates the value of local DTIM1 count which is enabled to be counted down when MPTCR1. PREDTIM_TRIG_EN
                                     SW is also able to set up the initial value for DTIM1 count-down by writing to this field.
    RESERVED24[28..24]           - (RO) Reserved bits
    TBTT1_CAL_BUSY[29]           - (RU) Calculates TBTT1 BUSY
    UPDATE_NEXT_TBTT1[30]        - (WO) Write:
                                     0: Meaningless
                                     1: NEXT_TBTT1_TIME is valid and to be updated.
    UPDATE_DTIM_COUNT1[31]       - (WO) Write:
                                     0: Meaningless
                                     1: DTIM_COUNT1 is valid and to be updated.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T1STR_UPDATE_DTIM_COUNT1_ADDR          BN0_WF_LPON_TOP_T1STR_ADDR
#define BN0_WF_LPON_TOP_T1STR_UPDATE_DTIM_COUNT1_MASK          0x80000000                // UPDATE_DTIM_COUNT1[31]
#define BN0_WF_LPON_TOP_T1STR_UPDATE_DTIM_COUNT1_SHFT          31
#define BN0_WF_LPON_TOP_T1STR_UPDATE_NEXT_TBTT1_ADDR           BN0_WF_LPON_TOP_T1STR_ADDR
#define BN0_WF_LPON_TOP_T1STR_UPDATE_NEXT_TBTT1_MASK           0x40000000                // UPDATE_NEXT_TBTT1[30]
#define BN0_WF_LPON_TOP_T1STR_UPDATE_NEXT_TBTT1_SHFT           30
#define BN0_WF_LPON_TOP_T1STR_TBTT1_CAL_BUSY_ADDR              BN0_WF_LPON_TOP_T1STR_ADDR
#define BN0_WF_LPON_TOP_T1STR_TBTT1_CAL_BUSY_MASK              0x20000000                // TBTT1_CAL_BUSY[29]
#define BN0_WF_LPON_TOP_T1STR_TBTT1_CAL_BUSY_SHFT              29
#define BN0_WF_LPON_TOP_T1STR_DTIM_COUNT1_ADDR                 BN0_WF_LPON_TOP_T1STR_ADDR
#define BN0_WF_LPON_TOP_T1STR_DTIM_COUNT1_MASK                 0x00FF0000                // DTIM_COUNT1[23..16]
#define BN0_WF_LPON_TOP_T1STR_DTIM_COUNT1_SHFT                 16
#define BN0_WF_LPON_TOP_T1STR_NEXT_TBTT1_TIME_ADDR             BN0_WF_LPON_TOP_T1STR_ADDR
#define BN0_WF_LPON_TOP_T1STR_NEXT_TBTT1_TIME_MASK             0x0000FFFF                // NEXT_TBTT1_TIME[15..0]
#define BN0_WF_LPON_TOP_T1STR_NEXT_TBTT1_TIME_SHFT             0

/* =====================================================================================

  ---T2STR (0x820EB000 + 0x0d0)---

    NEXT_TBTT2_TIME[15..0]       - (RU) Indicates the value of the next TBTT timer which is enabled to be counted down when MPTCR2. PREDTIM_TRIG_EN
                                     TBTT time is count in unit of TU compared to local TSF timer bit 25~11.
                                     Refer to TTPCR. TBTT_CAL_EN for how HW updates this value.
                                     SW is also able to set up the initial value, with TBTT time in unit of TU compared to TSF timer bit 5~11.
                                     Read: Next TBTT time in unit of TU
    DTIM_COUNT2[23..16]          - (RU) Indicates the value of local DTIM2 count which is enabled to be counted down when MPTCR2. PREDTIM_TRIG_EN
                                     SW is also able to set up the initial value for DTIM2 count-down by writing to this field.
    RESERVED24[28..24]           - (RO) Reserved bits
    TBTT2_CAL_BUSY[29]           - (RU) Calculates TBTT2 BUSY
    UPDATE_NEXT_TBTT2[30]        - (WO) Write:
                                     0: Meaningless
                                     1: NEXT_TBTT2_TIME is valid and to be updated.
    UPDATE_DTIM_COUNT2[31]       - (WO) Write:
                                     0: Meaningless
                                     1: DTIM_COUNT2 is valid and to be updated.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T2STR_UPDATE_DTIM_COUNT2_ADDR          BN0_WF_LPON_TOP_T2STR_ADDR
#define BN0_WF_LPON_TOP_T2STR_UPDATE_DTIM_COUNT2_MASK          0x80000000                // UPDATE_DTIM_COUNT2[31]
#define BN0_WF_LPON_TOP_T2STR_UPDATE_DTIM_COUNT2_SHFT          31
#define BN0_WF_LPON_TOP_T2STR_UPDATE_NEXT_TBTT2_ADDR           BN0_WF_LPON_TOP_T2STR_ADDR
#define BN0_WF_LPON_TOP_T2STR_UPDATE_NEXT_TBTT2_MASK           0x40000000                // UPDATE_NEXT_TBTT2[30]
#define BN0_WF_LPON_TOP_T2STR_UPDATE_NEXT_TBTT2_SHFT           30
#define BN0_WF_LPON_TOP_T2STR_TBTT2_CAL_BUSY_ADDR              BN0_WF_LPON_TOP_T2STR_ADDR
#define BN0_WF_LPON_TOP_T2STR_TBTT2_CAL_BUSY_MASK              0x20000000                // TBTT2_CAL_BUSY[29]
#define BN0_WF_LPON_TOP_T2STR_TBTT2_CAL_BUSY_SHFT              29
#define BN0_WF_LPON_TOP_T2STR_DTIM_COUNT2_ADDR                 BN0_WF_LPON_TOP_T2STR_ADDR
#define BN0_WF_LPON_TOP_T2STR_DTIM_COUNT2_MASK                 0x00FF0000                // DTIM_COUNT2[23..16]
#define BN0_WF_LPON_TOP_T2STR_DTIM_COUNT2_SHFT                 16
#define BN0_WF_LPON_TOP_T2STR_NEXT_TBTT2_TIME_ADDR             BN0_WF_LPON_TOP_T2STR_ADDR
#define BN0_WF_LPON_TOP_T2STR_NEXT_TBTT2_TIME_MASK             0x0000FFFF                // NEXT_TBTT2_TIME[15..0]
#define BN0_WF_LPON_TOP_T2STR_NEXT_TBTT2_TIME_SHFT             0

/* =====================================================================================

  ---T3STR (0x820EB000 + 0x0d4)---

    NEXT_TBTT3_TIME[15..0]       - (RU) Indicates the value of next TBTT timer which is enabled to be counted down when MPTCR3. PREDTIM_TRIG_EN
                                     TBTT time is count in unit of TU compared to local TSF timer bit 35~11.
                                     Refer to TTPCR. TBTT_CAL_EN for how HW updates this value.
                                     SW is also able to set up the initial value, with TBTT time in unit of TU compared to TSF timer bit35~11.
                                     Read: Next TBTT time in unit of TU
    DTIM_COUNT3[23..16]          - (RU) Indicates the value of local DTIM3 count which is enabled to be counted down when MPTCR3. PREDTIM_TRIG_EN
                                     SW is also able to set up the initial value for DTIM3 count-down by writing to this field.
    RESERVED24[28..24]           - (RO) Reserved bits
    TBTT3_CAL_BUSY[29]           - (RU) Calculates TBTT3 BUSY
    UPDATE_NEXT_TBTT3[30]        - (WO) Write:
                                     0: Meaningless
                                     1: NEXT_TBTT3_TIME is valid and to be updated.
    UPDATE_DTIM_COUNT3[31]       - (WO) Write:
                                     0: Meaningless
                                     1: DTIM_COUNT3 is valid and to be updated.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T3STR_UPDATE_DTIM_COUNT3_ADDR          BN0_WF_LPON_TOP_T3STR_ADDR
#define BN0_WF_LPON_TOP_T3STR_UPDATE_DTIM_COUNT3_MASK          0x80000000                // UPDATE_DTIM_COUNT3[31]
#define BN0_WF_LPON_TOP_T3STR_UPDATE_DTIM_COUNT3_SHFT          31
#define BN0_WF_LPON_TOP_T3STR_UPDATE_NEXT_TBTT3_ADDR           BN0_WF_LPON_TOP_T3STR_ADDR
#define BN0_WF_LPON_TOP_T3STR_UPDATE_NEXT_TBTT3_MASK           0x40000000                // UPDATE_NEXT_TBTT3[30]
#define BN0_WF_LPON_TOP_T3STR_UPDATE_NEXT_TBTT3_SHFT           30
#define BN0_WF_LPON_TOP_T3STR_TBTT3_CAL_BUSY_ADDR              BN0_WF_LPON_TOP_T3STR_ADDR
#define BN0_WF_LPON_TOP_T3STR_TBTT3_CAL_BUSY_MASK              0x20000000                // TBTT3_CAL_BUSY[29]
#define BN0_WF_LPON_TOP_T3STR_TBTT3_CAL_BUSY_SHFT              29
#define BN0_WF_LPON_TOP_T3STR_DTIM_COUNT3_ADDR                 BN0_WF_LPON_TOP_T3STR_ADDR
#define BN0_WF_LPON_TOP_T3STR_DTIM_COUNT3_MASK                 0x00FF0000                // DTIM_COUNT3[23..16]
#define BN0_WF_LPON_TOP_T3STR_DTIM_COUNT3_SHFT                 16
#define BN0_WF_LPON_TOP_T3STR_NEXT_TBTT3_TIME_ADDR             BN0_WF_LPON_TOP_T3STR_ADDR
#define BN0_WF_LPON_TOP_T3STR_NEXT_TBTT3_TIME_MASK             0x0000FFFF                // NEXT_TBTT3_TIME[15..0]
#define BN0_WF_LPON_TOP_T3STR_NEXT_TBTT3_TIME_SHFT             0

/* =====================================================================================

  ---T0TPCR (0x820EB000 + 0x0d8)---

    BEACONPERIOD0[15..0]         - (RW) Indicates beacon interval for TBTT, PreTBTT and PreDTIM timer
                                     Unit: TU
    DTIMPERIOD0[23..16]          - (RW) Indicates the number of beacon interval between successive DTIMs as specified in beacon
                                     0: Disable this wakeup function
    TBTTWAKEPERIOD0[27..24]      - (RW) Indicates the number of TBTT to wake up from sleep state only
                                     0: Disable this wakeup function. MT7615 will wake up when the local TBTT wake counter decreases to 0. The function after wakeup due to this counter will be controlled by the same scheme for DTIM function.
    DTIMWAKEPERIOD0[30..28]      - (RW) Indicates the number of DTIM to wake up from sleep state only
                                     0: Disable DTIM wakeup function. MT7615 will wake up when the local DTIM wake counter decreases to 0. The function after wakeup due to this counter will be controlled by the same scheme for DTIM function.
    TBTT0_CAL_EN[31]             - (RW) When this function is enabled, HW will calculate the initial NEXT_TBTT_TIME based on the current TSF and will also update it when TSF is updated on TSF abnormal situation.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T0TPCR_TBTT0_CAL_EN_ADDR               BN0_WF_LPON_TOP_T0TPCR_ADDR
#define BN0_WF_LPON_TOP_T0TPCR_TBTT0_CAL_EN_MASK               0x80000000                // TBTT0_CAL_EN[31]
#define BN0_WF_LPON_TOP_T0TPCR_TBTT0_CAL_EN_SHFT               31
#define BN0_WF_LPON_TOP_T0TPCR_DTIMWAKEPERIOD0_ADDR            BN0_WF_LPON_TOP_T0TPCR_ADDR
#define BN0_WF_LPON_TOP_T0TPCR_DTIMWAKEPERIOD0_MASK            0x70000000                // DTIMWAKEPERIOD0[30..28]
#define BN0_WF_LPON_TOP_T0TPCR_DTIMWAKEPERIOD0_SHFT            28
#define BN0_WF_LPON_TOP_T0TPCR_TBTTWAKEPERIOD0_ADDR            BN0_WF_LPON_TOP_T0TPCR_ADDR
#define BN0_WF_LPON_TOP_T0TPCR_TBTTWAKEPERIOD0_MASK            0x0F000000                // TBTTWAKEPERIOD0[27..24]
#define BN0_WF_LPON_TOP_T0TPCR_TBTTWAKEPERIOD0_SHFT            24
#define BN0_WF_LPON_TOP_T0TPCR_DTIMPERIOD0_ADDR                BN0_WF_LPON_TOP_T0TPCR_ADDR
#define BN0_WF_LPON_TOP_T0TPCR_DTIMPERIOD0_MASK                0x00FF0000                // DTIMPERIOD0[23..16]
#define BN0_WF_LPON_TOP_T0TPCR_DTIMPERIOD0_SHFT                16
#define BN0_WF_LPON_TOP_T0TPCR_BEACONPERIOD0_ADDR              BN0_WF_LPON_TOP_T0TPCR_ADDR
#define BN0_WF_LPON_TOP_T0TPCR_BEACONPERIOD0_MASK              0x0000FFFF                // BEACONPERIOD0[15..0]
#define BN0_WF_LPON_TOP_T0TPCR_BEACONPERIOD0_SHFT              0

/* =====================================================================================

  ---T1TPCR (0x820EB000 + 0x0dc)---

    BEACONPERIOD1[15..0]         - (RW) Indicates beacon interval for TBTT, PreTBTT and PreDTIM timer
                                     Unit: TU
    DTIMPERIOD1[23..16]          - (RW) Indicates the number of beacon interval between successive DTIMs as specified in beacon
                                     0: Disable this wakeup function
    TBTTWAKEPERIOD1[27..24]      - (RW) Indicates the number of TBTT to wake up from sleep state only
                                     0: Disable this wakeup function. MT7615 will wake up when the local TBTT wake counter decreases to 0. The function after wakeup due to this counter will be controlled by the same scheme for DTIM function.
    DTIMWAKEPERIOD1[30..28]      - (RW) Indicates the number of DTIM to wake up from sleep state only
                                     0: Disable DTIM wakeup function. MT7615 will wake up when the local DTIM wake counter decreases to 0. The function after wakeup due to this counter will be controlled by the same scheme for DTIM function.
    TBTT1_CAL_EN[31]             - (RW) When this function is enabled, HW will calculate the initial NEXT_TBTT_TIME based on the current TSF and will also update it when TSF is updated on TSF abnormal situation.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T1TPCR_TBTT1_CAL_EN_ADDR               BN0_WF_LPON_TOP_T1TPCR_ADDR
#define BN0_WF_LPON_TOP_T1TPCR_TBTT1_CAL_EN_MASK               0x80000000                // TBTT1_CAL_EN[31]
#define BN0_WF_LPON_TOP_T1TPCR_TBTT1_CAL_EN_SHFT               31
#define BN0_WF_LPON_TOP_T1TPCR_DTIMWAKEPERIOD1_ADDR            BN0_WF_LPON_TOP_T1TPCR_ADDR
#define BN0_WF_LPON_TOP_T1TPCR_DTIMWAKEPERIOD1_MASK            0x70000000                // DTIMWAKEPERIOD1[30..28]
#define BN0_WF_LPON_TOP_T1TPCR_DTIMWAKEPERIOD1_SHFT            28
#define BN0_WF_LPON_TOP_T1TPCR_TBTTWAKEPERIOD1_ADDR            BN0_WF_LPON_TOP_T1TPCR_ADDR
#define BN0_WF_LPON_TOP_T1TPCR_TBTTWAKEPERIOD1_MASK            0x0F000000                // TBTTWAKEPERIOD1[27..24]
#define BN0_WF_LPON_TOP_T1TPCR_TBTTWAKEPERIOD1_SHFT            24
#define BN0_WF_LPON_TOP_T1TPCR_DTIMPERIOD1_ADDR                BN0_WF_LPON_TOP_T1TPCR_ADDR
#define BN0_WF_LPON_TOP_T1TPCR_DTIMPERIOD1_MASK                0x00FF0000                // DTIMPERIOD1[23..16]
#define BN0_WF_LPON_TOP_T1TPCR_DTIMPERIOD1_SHFT                16
#define BN0_WF_LPON_TOP_T1TPCR_BEACONPERIOD1_ADDR              BN0_WF_LPON_TOP_T1TPCR_ADDR
#define BN0_WF_LPON_TOP_T1TPCR_BEACONPERIOD1_MASK              0x0000FFFF                // BEACONPERIOD1[15..0]
#define BN0_WF_LPON_TOP_T1TPCR_BEACONPERIOD1_SHFT              0

/* =====================================================================================

  ---T2TPCR (0x820EB000 + 0x0e0)---

    BEACONPERIOD2[15..0]         - (RW) Indicates the beacon interval for TBTT, PreTBTT and PreDTIM timer
                                     Unit: TU
    DTIMPERIOD2[23..16]          - (RW) Indicates the number of beacon interval between successive DTIMs as specified in beacon
                                     0: Disable this wakeup function
    TBTTWAKEPERIOD2[27..24]      - (RW) Indicates the number of TBTT to wake up from sleep state only
                                     0: Disable this wakeup function. MT7615 will wake up when the local TBTT wake counter decreases to 0. The function after wakeup due to this counter will be controlled by the same scheme for DTIM function.
    DTIMWAKEPERIOD2[30..28]      - (RW) Indicates the number of DTIM to wake up from sleep state only
                                     0: Disable DTIM wakeup function. MT7615 will wake up when the local DTIM wake counter decreases to 0. The function after wakeup due to this counter will be controlled by the same scheme for DTIM function.
    TBTT2_CAL_EN[31]             - (RW) When this function is enabled, HW will calculate the initial NEXT_TBTT_TIME based on the current TSF and will update it when TSF is updated on TSF abnormal situation.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T2TPCR_TBTT2_CAL_EN_ADDR               BN0_WF_LPON_TOP_T2TPCR_ADDR
#define BN0_WF_LPON_TOP_T2TPCR_TBTT2_CAL_EN_MASK               0x80000000                // TBTT2_CAL_EN[31]
#define BN0_WF_LPON_TOP_T2TPCR_TBTT2_CAL_EN_SHFT               31
#define BN0_WF_LPON_TOP_T2TPCR_DTIMWAKEPERIOD2_ADDR            BN0_WF_LPON_TOP_T2TPCR_ADDR
#define BN0_WF_LPON_TOP_T2TPCR_DTIMWAKEPERIOD2_MASK            0x70000000                // DTIMWAKEPERIOD2[30..28]
#define BN0_WF_LPON_TOP_T2TPCR_DTIMWAKEPERIOD2_SHFT            28
#define BN0_WF_LPON_TOP_T2TPCR_TBTTWAKEPERIOD2_ADDR            BN0_WF_LPON_TOP_T2TPCR_ADDR
#define BN0_WF_LPON_TOP_T2TPCR_TBTTWAKEPERIOD2_MASK            0x0F000000                // TBTTWAKEPERIOD2[27..24]
#define BN0_WF_LPON_TOP_T2TPCR_TBTTWAKEPERIOD2_SHFT            24
#define BN0_WF_LPON_TOP_T2TPCR_DTIMPERIOD2_ADDR                BN0_WF_LPON_TOP_T2TPCR_ADDR
#define BN0_WF_LPON_TOP_T2TPCR_DTIMPERIOD2_MASK                0x00FF0000                // DTIMPERIOD2[23..16]
#define BN0_WF_LPON_TOP_T2TPCR_DTIMPERIOD2_SHFT                16
#define BN0_WF_LPON_TOP_T2TPCR_BEACONPERIOD2_ADDR              BN0_WF_LPON_TOP_T2TPCR_ADDR
#define BN0_WF_LPON_TOP_T2TPCR_BEACONPERIOD2_MASK              0x0000FFFF                // BEACONPERIOD2[15..0]
#define BN0_WF_LPON_TOP_T2TPCR_BEACONPERIOD2_SHFT              0

/* =====================================================================================

  ---T3TPCR (0x820EB000 + 0x0e4)---

    BEACONPERIOD3[15..0]         - (RW) Indicates the beacon interval for TBTT, PreTBTT and PreDTIM timer
                                     Unit: TU
    DTIMPERIOD3[23..16]          - (RW) Indicates the number of beacon interval between successive DTIMs as specified in beacon
                                     0: Disable this wakeup function
    TBTTWAKEPERIOD3[27..24]      - (RW) Indicates the number of TBTT to wake up from sleep state only
                                     0: Disable this wakeup function. MT7615 will wake up when the local TBTT wake counter decreases to 0. The function after wakeup due to this counter will be controlled by the same scheme for DTIM function.
    DTIMWAKEPERIOD3[30..28]      - (RW) Indicates the number of DTIM to wake up from sleep state only
                                     0: Disable DTIM wakeup function. MT7615 will wake up when the local DTIM wake counter decreases to 0. The function after wakeup due to this counter will be controlled by the same scheme for DTIM function.
    TBTT3_CAL_EN[31]             - (RW) When this function is enabled, HW will calculate the initial NEXT_TBTT_TIME based on the current TSF and will update it when TSF is updated on TSF abnormal situation.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T3TPCR_TBTT3_CAL_EN_ADDR               BN0_WF_LPON_TOP_T3TPCR_ADDR
#define BN0_WF_LPON_TOP_T3TPCR_TBTT3_CAL_EN_MASK               0x80000000                // TBTT3_CAL_EN[31]
#define BN0_WF_LPON_TOP_T3TPCR_TBTT3_CAL_EN_SHFT               31
#define BN0_WF_LPON_TOP_T3TPCR_DTIMWAKEPERIOD3_ADDR            BN0_WF_LPON_TOP_T3TPCR_ADDR
#define BN0_WF_LPON_TOP_T3TPCR_DTIMWAKEPERIOD3_MASK            0x70000000                // DTIMWAKEPERIOD3[30..28]
#define BN0_WF_LPON_TOP_T3TPCR_DTIMWAKEPERIOD3_SHFT            28
#define BN0_WF_LPON_TOP_T3TPCR_TBTTWAKEPERIOD3_ADDR            BN0_WF_LPON_TOP_T3TPCR_ADDR
#define BN0_WF_LPON_TOP_T3TPCR_TBTTWAKEPERIOD3_MASK            0x0F000000                // TBTTWAKEPERIOD3[27..24]
#define BN0_WF_LPON_TOP_T3TPCR_TBTTWAKEPERIOD3_SHFT            24
#define BN0_WF_LPON_TOP_T3TPCR_DTIMPERIOD3_ADDR                BN0_WF_LPON_TOP_T3TPCR_ADDR
#define BN0_WF_LPON_TOP_T3TPCR_DTIMPERIOD3_MASK                0x00FF0000                // DTIMPERIOD3[23..16]
#define BN0_WF_LPON_TOP_T3TPCR_DTIMPERIOD3_SHFT                16
#define BN0_WF_LPON_TOP_T3TPCR_BEACONPERIOD3_ADDR              BN0_WF_LPON_TOP_T3TPCR_ADDR
#define BN0_WF_LPON_TOP_T3TPCR_BEACONPERIOD3_MASK              0x0000FFFF                // BEACONPERIOD3[15..0]
#define BN0_WF_LPON_TOP_T3TPCR_BEACONPERIOD3_SHFT              0

/* =====================================================================================

  ---TT0STR (0x820EB000 + 0x0e8)---

    NEXT_TTTT0_TIME[25..0]       - (RU) Indicates the value of the next TTTT timer which is enabled to be counted down when MPTCR4.PRETTTT0_TRIG_EN
                                     TBTT time is count in unit of us compared to local TSF timer bit25~0.
                                     Refer to TTPCR. TTTT_CAL_EN for how HW updates this value.
                                     SW is also able to set up the initial value, with TBTT time in unit of us compared to TSF timer bit25~0.
                                     Read: Next TTTT time in unit of us
    RESERVED26[29..26]           - (RO) Reserved bits
    UPDATE_NEXT_TTTT0[30]        - (WO) Write:
                                     0: Meaningless
                                     1: NEXT_TTTT0_TIME is valid and to be updated.
    TTTT0_CAL_BUSY[31]           - (RU) Calculates TTTT0 BUSY

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0STR_TTTT0_CAL_BUSY_ADDR             BN0_WF_LPON_TOP_TT0STR_ADDR
#define BN0_WF_LPON_TOP_TT0STR_TTTT0_CAL_BUSY_MASK             0x80000000                // TTTT0_CAL_BUSY[31]
#define BN0_WF_LPON_TOP_TT0STR_TTTT0_CAL_BUSY_SHFT             31
#define BN0_WF_LPON_TOP_TT0STR_UPDATE_NEXT_TTTT0_ADDR          BN0_WF_LPON_TOP_TT0STR_ADDR
#define BN0_WF_LPON_TOP_TT0STR_UPDATE_NEXT_TTTT0_MASK          0x40000000                // UPDATE_NEXT_TTTT0[30]
#define BN0_WF_LPON_TOP_TT0STR_UPDATE_NEXT_TTTT0_SHFT          30
#define BN0_WF_LPON_TOP_TT0STR_NEXT_TTTT0_TIME_ADDR            BN0_WF_LPON_TOP_TT0STR_ADDR
#define BN0_WF_LPON_TOP_TT0STR_NEXT_TTTT0_TIME_MASK            0x03FFFFFF                // NEXT_TTTT0_TIME[25..0]
#define BN0_WF_LPON_TOP_TT0STR_NEXT_TTTT0_TIME_SHFT            0

/* =====================================================================================

  ---TT1STR (0x820EB000 + 0x0ec)---

    NEXT_TTTT1_TIME[25..0]       - (RU) Indicates the value of the next TTTT timer which is enabled to be counted down when MPTCR4.PRETTTT1_TRIG_EN
                                     TBTT time is count in unit of us compared to local TSF timer bit25~0.
                                     Refer to TTPCR. TTTT_CAL_EN for how HW updates this value.
                                     SW is also able to set up the initial value, with TBTT time in unit of us compared to TSF timer bit25~0.
                                     Read: Next TTTT time in unit of us
    RESERVED26[29..26]           - (RO) Reserved bits
    UPDATE_NEXT_TTTT1[30]        - (WO) Write:
                                     0: Meaningless
                                     1: NEXT_TTTT1_TIME is valid and to be updated.
    TTTT1_CAL_BUSY[31]           - (RU) Calculates TTTT1 BUSY

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT1STR_TTTT1_CAL_BUSY_ADDR             BN0_WF_LPON_TOP_TT1STR_ADDR
#define BN0_WF_LPON_TOP_TT1STR_TTTT1_CAL_BUSY_MASK             0x80000000                // TTTT1_CAL_BUSY[31]
#define BN0_WF_LPON_TOP_TT1STR_TTTT1_CAL_BUSY_SHFT             31
#define BN0_WF_LPON_TOP_TT1STR_UPDATE_NEXT_TTTT1_ADDR          BN0_WF_LPON_TOP_TT1STR_ADDR
#define BN0_WF_LPON_TOP_TT1STR_UPDATE_NEXT_TTTT1_MASK          0x40000000                // UPDATE_NEXT_TTTT1[30]
#define BN0_WF_LPON_TOP_TT1STR_UPDATE_NEXT_TTTT1_SHFT          30
#define BN0_WF_LPON_TOP_TT1STR_NEXT_TTTT1_TIME_ADDR            BN0_WF_LPON_TOP_TT1STR_ADDR
#define BN0_WF_LPON_TOP_TT1STR_NEXT_TTTT1_TIME_MASK            0x03FFFFFF                // NEXT_TTTT1_TIME[25..0]
#define BN0_WF_LPON_TOP_TT1STR_NEXT_TTTT1_TIME_SHFT            0

/* =====================================================================================

  ---TT2STR (0x820EB000 + 0x0f0)---

    NEXT_TTTT2_TIME[25..0]       - (RU) Indicates the value of the next TTTT timer which is enabled to be counted down when MPTCR6.PRETTTT2_TRIG_EN
                                     TBTT time is count in unit of us compared to local TSF timer bit25~0.
                                     Refer to TTPCR. TTTT_CAL_EN for how HW updates this value.
                                     SW is also able to set up the initial value, with TBTT time in unit of us compared to TSF timer bit25~0.
                                     Read: Next TTTT time in unit of us
    RESERVED26[29..26]           - (RO) Reserved bits
    UPDATE_NEXT_TTTT2[30]        - (WO) Write:
                                     0: Meaningless
                                     1: NEXT_TTTT2_TIME is valid and to be updated.
    TTTT2_CAL_BUSY[31]           - (RU) Calculates TTTT2 BUSY

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT2STR_TTTT2_CAL_BUSY_ADDR             BN0_WF_LPON_TOP_TT2STR_ADDR
#define BN0_WF_LPON_TOP_TT2STR_TTTT2_CAL_BUSY_MASK             0x80000000                // TTTT2_CAL_BUSY[31]
#define BN0_WF_LPON_TOP_TT2STR_TTTT2_CAL_BUSY_SHFT             31
#define BN0_WF_LPON_TOP_TT2STR_UPDATE_NEXT_TTTT2_ADDR          BN0_WF_LPON_TOP_TT2STR_ADDR
#define BN0_WF_LPON_TOP_TT2STR_UPDATE_NEXT_TTTT2_MASK          0x40000000                // UPDATE_NEXT_TTTT2[30]
#define BN0_WF_LPON_TOP_TT2STR_UPDATE_NEXT_TTTT2_SHFT          30
#define BN0_WF_LPON_TOP_TT2STR_NEXT_TTTT2_TIME_ADDR            BN0_WF_LPON_TOP_TT2STR_ADDR
#define BN0_WF_LPON_TOP_TT2STR_NEXT_TTTT2_TIME_MASK            0x03FFFFFF                // NEXT_TTTT2_TIME[25..0]
#define BN0_WF_LPON_TOP_TT2STR_NEXT_TTTT2_TIME_SHFT            0

/* =====================================================================================

  ---TT3STR (0x820EB000 + 0x0f4)---

    NEXT_TTTT3_TIME[25..0]       - (RU) Indicates the value of the next TTTT timer which is enabled to be counted down when MPTCR6.PRETTTT3_TRIG_EN
                                     TBTT time is count in unit of us compared to local TSF timer bit25~0.
                                     Refer to TTPCR. TTTT_CAL_EN for how HW updates this value.
                                     SW is also able to set up the initial value, with TBTT time in unit of us compared to TSF timer bit25~0.
                                     Read: Next TTTT time in unit of us
    RESERVED26[29..26]           - (RO) Reserved bits
    UPDATE_NEXT_TTTT3[30]        - (WO) Write:
                                     0: Meaningless
                                     1: NEXT_TTTT3_TIME is valid and to be updated.
    TTTT3_CAL_BUSY[31]           - (RU) Calculates TTTT3 BUSY

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT3STR_TTTT3_CAL_BUSY_ADDR             BN0_WF_LPON_TOP_TT3STR_ADDR
#define BN0_WF_LPON_TOP_TT3STR_TTTT3_CAL_BUSY_MASK             0x80000000                // TTTT3_CAL_BUSY[31]
#define BN0_WF_LPON_TOP_TT3STR_TTTT3_CAL_BUSY_SHFT             31
#define BN0_WF_LPON_TOP_TT3STR_UPDATE_NEXT_TTTT3_ADDR          BN0_WF_LPON_TOP_TT3STR_ADDR
#define BN0_WF_LPON_TOP_TT3STR_UPDATE_NEXT_TTTT3_MASK          0x40000000                // UPDATE_NEXT_TTTT3[30]
#define BN0_WF_LPON_TOP_TT3STR_UPDATE_NEXT_TTTT3_SHFT          30
#define BN0_WF_LPON_TOP_TT3STR_NEXT_TTTT3_TIME_ADDR            BN0_WF_LPON_TOP_TT3STR_ADDR
#define BN0_WF_LPON_TOP_TT3STR_NEXT_TTTT3_TIME_MASK            0x03FFFFFF                // NEXT_TTTT3_TIME[25..0]
#define BN0_WF_LPON_TOP_TT3STR_NEXT_TTTT3_TIME_SHFT            0

/* =====================================================================================

  ---TT0TPCR (0x820EB000 + 0x0f8)---

    TTTT0_OFFSET_OF_TBTT0[19..0] - (RW) Indicates TTTT0 (Target TIM Transmission Time) offset of TBTT0
                                     Unit: 1us
                                     Range: -534288~534287 us
    RESERVED20[28..20]           - (RO) Reserved bits
    TTTT0_UPDATE_DTIM[29]        - (RW) This field indicates the enable for updating DTIM of corresponded BSSID tim broadcast
                                     0: not update
                                     1: update it
    TTTT0_UPDATE_TSF[30]         - (RW) This field indicates the enable for updating TSF of corresponded BSSID tim broadcast 
                                     0: not update
                                     1: update it
    TTTT0_CAL_EN[31]             - (RW) TTTT0 calculation enable bit

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0TPCR_TTTT0_CAL_EN_ADDR              BN0_WF_LPON_TOP_TT0TPCR_ADDR
#define BN0_WF_LPON_TOP_TT0TPCR_TTTT0_CAL_EN_MASK              0x80000000                // TTTT0_CAL_EN[31]
#define BN0_WF_LPON_TOP_TT0TPCR_TTTT0_CAL_EN_SHFT              31
#define BN0_WF_LPON_TOP_TT0TPCR_TTTT0_UPDATE_TSF_ADDR          BN0_WF_LPON_TOP_TT0TPCR_ADDR
#define BN0_WF_LPON_TOP_TT0TPCR_TTTT0_UPDATE_TSF_MASK          0x40000000                // TTTT0_UPDATE_TSF[30]
#define BN0_WF_LPON_TOP_TT0TPCR_TTTT0_UPDATE_TSF_SHFT          30
#define BN0_WF_LPON_TOP_TT0TPCR_TTTT0_UPDATE_DTIM_ADDR         BN0_WF_LPON_TOP_TT0TPCR_ADDR
#define BN0_WF_LPON_TOP_TT0TPCR_TTTT0_UPDATE_DTIM_MASK         0x20000000                // TTTT0_UPDATE_DTIM[29]
#define BN0_WF_LPON_TOP_TT0TPCR_TTTT0_UPDATE_DTIM_SHFT         29
#define BN0_WF_LPON_TOP_TT0TPCR_TTTT0_OFFSET_OF_TBTT0_ADDR     BN0_WF_LPON_TOP_TT0TPCR_ADDR
#define BN0_WF_LPON_TOP_TT0TPCR_TTTT0_OFFSET_OF_TBTT0_MASK     0x000FFFFF                // TTTT0_OFFSET_OF_TBTT0[19..0]
#define BN0_WF_LPON_TOP_TT0TPCR_TTTT0_OFFSET_OF_TBTT0_SHFT     0

/* =====================================================================================

  ---TT1TPCR (0x820EB000 + 0x0fc)---

    TTTT1_OFFSET_OF_TBTT1[19..0] - (RW) Indicates TTTT1 (Target TIM Transmission Time) offset of TBTT1
                                     Unit: 1us
                                     Range: -534288~534287 us
    RESERVED20[28..20]           - (RO) Reserved bits
    TTTT1_UPDATE_DTIM[29]        - (RW) This field indicates the enable for updating DTIM of corresponded BSSID tim broadcast
                                     0: not update
                                     1: update it
    TTTT1_UPDATE_TSF[30]         - (RW) This field indicates the enable for updating TSF of corresponded BSSID tim broadcast 
                                     0: not update
                                     1: update it
    TTTT1_CAL_EN[31]             - (RW) TTTT1 calculation enable bit

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT1TPCR_TTTT1_CAL_EN_ADDR              BN0_WF_LPON_TOP_TT1TPCR_ADDR
#define BN0_WF_LPON_TOP_TT1TPCR_TTTT1_CAL_EN_MASK              0x80000000                // TTTT1_CAL_EN[31]
#define BN0_WF_LPON_TOP_TT1TPCR_TTTT1_CAL_EN_SHFT              31
#define BN0_WF_LPON_TOP_TT1TPCR_TTTT1_UPDATE_TSF_ADDR          BN0_WF_LPON_TOP_TT1TPCR_ADDR
#define BN0_WF_LPON_TOP_TT1TPCR_TTTT1_UPDATE_TSF_MASK          0x40000000                // TTTT1_UPDATE_TSF[30]
#define BN0_WF_LPON_TOP_TT1TPCR_TTTT1_UPDATE_TSF_SHFT          30
#define BN0_WF_LPON_TOP_TT1TPCR_TTTT1_UPDATE_DTIM_ADDR         BN0_WF_LPON_TOP_TT1TPCR_ADDR
#define BN0_WF_LPON_TOP_TT1TPCR_TTTT1_UPDATE_DTIM_MASK         0x20000000                // TTTT1_UPDATE_DTIM[29]
#define BN0_WF_LPON_TOP_TT1TPCR_TTTT1_UPDATE_DTIM_SHFT         29
#define BN0_WF_LPON_TOP_TT1TPCR_TTTT1_OFFSET_OF_TBTT1_ADDR     BN0_WF_LPON_TOP_TT1TPCR_ADDR
#define BN0_WF_LPON_TOP_TT1TPCR_TTTT1_OFFSET_OF_TBTT1_MASK     0x000FFFFF                // TTTT1_OFFSET_OF_TBTT1[19..0]
#define BN0_WF_LPON_TOP_TT1TPCR_TTTT1_OFFSET_OF_TBTT1_SHFT     0

/* =====================================================================================

  ---TT2TPCR (0x820EB000 + 0x100)---

    TTTT2_OFFSET_OF_TBTT2[19..0] - (RW) Indicates TTTT2 (Target TIM Transmission Time) offset of TBTT2
                                     Unit: 1us
                                     Range: -534288~534287 us
    RESERVED20[28..20]           - (RO) Reserved bits
    TTTT2_UPDATE_DTIM[29]        - (RW) This field indicates the enable for updating DTIM of corresponded BSSID tim broadcast
                                     0: not update
                                     1: update it
    TTTT2_UPDATE_TSF[30]         - (RW) This field indicates the enable for updating TSF of corresponded BSSID tim broadcast 
                                     0: not update
                                     1: update it
    TTTT2_CAL_EN[31]             - (RW) TTTT2 calculation enable bit

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT2TPCR_TTTT2_CAL_EN_ADDR              BN0_WF_LPON_TOP_TT2TPCR_ADDR
#define BN0_WF_LPON_TOP_TT2TPCR_TTTT2_CAL_EN_MASK              0x80000000                // TTTT2_CAL_EN[31]
#define BN0_WF_LPON_TOP_TT2TPCR_TTTT2_CAL_EN_SHFT              31
#define BN0_WF_LPON_TOP_TT2TPCR_TTTT2_UPDATE_TSF_ADDR          BN0_WF_LPON_TOP_TT2TPCR_ADDR
#define BN0_WF_LPON_TOP_TT2TPCR_TTTT2_UPDATE_TSF_MASK          0x40000000                // TTTT2_UPDATE_TSF[30]
#define BN0_WF_LPON_TOP_TT2TPCR_TTTT2_UPDATE_TSF_SHFT          30
#define BN0_WF_LPON_TOP_TT2TPCR_TTTT2_UPDATE_DTIM_ADDR         BN0_WF_LPON_TOP_TT2TPCR_ADDR
#define BN0_WF_LPON_TOP_TT2TPCR_TTTT2_UPDATE_DTIM_MASK         0x20000000                // TTTT2_UPDATE_DTIM[29]
#define BN0_WF_LPON_TOP_TT2TPCR_TTTT2_UPDATE_DTIM_SHFT         29
#define BN0_WF_LPON_TOP_TT2TPCR_TTTT2_OFFSET_OF_TBTT2_ADDR     BN0_WF_LPON_TOP_TT2TPCR_ADDR
#define BN0_WF_LPON_TOP_TT2TPCR_TTTT2_OFFSET_OF_TBTT2_MASK     0x000FFFFF                // TTTT2_OFFSET_OF_TBTT2[19..0]
#define BN0_WF_LPON_TOP_TT2TPCR_TTTT2_OFFSET_OF_TBTT2_SHFT     0

/* =====================================================================================

  ---TT3TPCR (0x820EB000 + 0x104)---

    TTTT3_OFFSET_OF_TBTT3[19..0] - (RW) Indicates TTTT3 (Target TIM Transmission Time) offset of TBTT3
                                     Unit: 1us
                                     Range: -534288~534287 us
    RESERVED20[28..20]           - (RO) Reserved bits
    TTTT3_UPDATE_DTIM[29]        - (RW) This field indicates the enable for updating DTIM of corresponded BSSID tim broadcast
                                     0: not update
                                     1: update it
    TTTT3_UPDATE_TSF[30]         - (RW) This field indicates the enable for updating TSF of corresponded BSSID tim broadcast 
                                     0: not update
                                     1: update it
    TTTT3_CAL_EN[31]             - (RW) TTTT3 calculation enable bit

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT3TPCR_TTTT3_CAL_EN_ADDR              BN0_WF_LPON_TOP_TT3TPCR_ADDR
#define BN0_WF_LPON_TOP_TT3TPCR_TTTT3_CAL_EN_MASK              0x80000000                // TTTT3_CAL_EN[31]
#define BN0_WF_LPON_TOP_TT3TPCR_TTTT3_CAL_EN_SHFT              31
#define BN0_WF_LPON_TOP_TT3TPCR_TTTT3_UPDATE_TSF_ADDR          BN0_WF_LPON_TOP_TT3TPCR_ADDR
#define BN0_WF_LPON_TOP_TT3TPCR_TTTT3_UPDATE_TSF_MASK          0x40000000                // TTTT3_UPDATE_TSF[30]
#define BN0_WF_LPON_TOP_TT3TPCR_TTTT3_UPDATE_TSF_SHFT          30
#define BN0_WF_LPON_TOP_TT3TPCR_TTTT3_UPDATE_DTIM_ADDR         BN0_WF_LPON_TOP_TT3TPCR_ADDR
#define BN0_WF_LPON_TOP_TT3TPCR_TTTT3_UPDATE_DTIM_MASK         0x20000000                // TTTT3_UPDATE_DTIM[29]
#define BN0_WF_LPON_TOP_TT3TPCR_TTTT3_UPDATE_DTIM_SHFT         29
#define BN0_WF_LPON_TOP_TT3TPCR_TTTT3_OFFSET_OF_TBTT3_ADDR     BN0_WF_LPON_TOP_TT3TPCR_ADDR
#define BN0_WF_LPON_TOP_TT3TPCR_TTTT3_OFFSET_OF_TBTT3_MASK     0x000FFFFF                // TTTT3_OFFSET_OF_TBTT3[19..0]
#define BN0_WF_LPON_TOP_TT3TPCR_TTTT3_OFFSET_OF_TBTT3_SHFT     0

/* =====================================================================================

  ---TT4TPCR (0x820EB000 + 0x108)---

    TIM_PERIOD0[23..0]           - (RW) TTTT0 TIM period INTERVAL, n<=255
                                     TIM period = TTTT interval*Beacon interval
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT4TPCR_TIM_PERIOD0_ADDR               BN0_WF_LPON_TOP_TT4TPCR_ADDR
#define BN0_WF_LPON_TOP_TT4TPCR_TIM_PERIOD0_MASK               0x00FFFFFF                // TIM_PERIOD0[23..0]
#define BN0_WF_LPON_TOP_TT4TPCR_TIM_PERIOD0_SHFT               0

/* =====================================================================================

  ---TT5TPCR (0x820EB000 + 0x10c)---

    TIM_PERIOD1[23..0]           - (RW) TTTT1 TIM period INTERVAL, n<=255
                                     TIM period = TTTT interval*Beacon interval
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT5TPCR_TIM_PERIOD1_ADDR               BN0_WF_LPON_TOP_TT5TPCR_ADDR
#define BN0_WF_LPON_TOP_TT5TPCR_TIM_PERIOD1_MASK               0x00FFFFFF                // TIM_PERIOD1[23..0]
#define BN0_WF_LPON_TOP_TT5TPCR_TIM_PERIOD1_SHFT               0

/* =====================================================================================

  ---TT6TPCR (0x820EB000 + 0x110)---

    TIM_PERIOD2[23..0]           - (RW) TTTT2 TIM period INTERVAL, n<=255
                                     TIM period = TTTT interval*Beacon interval
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT6TPCR_TIM_PERIOD2_ADDR               BN0_WF_LPON_TOP_TT6TPCR_ADDR
#define BN0_WF_LPON_TOP_TT6TPCR_TIM_PERIOD2_MASK               0x00FFFFFF                // TIM_PERIOD2[23..0]
#define BN0_WF_LPON_TOP_TT6TPCR_TIM_PERIOD2_SHFT               0

/* =====================================================================================

  ---TT7TPCR (0x820EB000 + 0x114)---

    TIM_PERIOD3[23..0]           - (RW) TTTT3 TIM period INTERVAL, n<=255
                                     TIM period = TTTT interval*Beacon interval
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT7TPCR_TIM_PERIOD3_ADDR               BN0_WF_LPON_TOP_TT7TPCR_ADDR
#define BN0_WF_LPON_TOP_TT7TPCR_TIM_PERIOD3_MASK               0x00FFFFFF                // TIM_PERIOD3[23..0]
#define BN0_WF_LPON_TOP_TT7TPCR_TIM_PERIOD3_SHFT               0

/* =====================================================================================

  ---T0SFR (0x820EB000 + 0x118)---

    EARLIER_TBTT0_OFFSET[15..0]  - (RW) Time offset to compensate by subtracting original HW calculated TBTT (in NEXT_TBTT0_TIME field)
                                     Unit: TU
                                     The following TBTT and related function will be triggered by this modified timing. This field is only valid when non-zero value in this field is specified; it will not affect the original TBTT calibration or related functions. It will not affect the TBTT value set by SW, either.
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T0SFR_EARLIER_TBTT0_OFFSET_ADDR        BN0_WF_LPON_TOP_T0SFR_ADDR
#define BN0_WF_LPON_TOP_T0SFR_EARLIER_TBTT0_OFFSET_MASK        0x0000FFFF                // EARLIER_TBTT0_OFFSET[15..0]
#define BN0_WF_LPON_TOP_T0SFR_EARLIER_TBTT0_OFFSET_SHFT        0

/* =====================================================================================

  ---T1SFR (0x820EB000 + 0x11c)---

    EARLIER_TBTT1_OFFSET[15..0]  - (RW) Time offset to compensate by subtracting original HW calculated TBTT (in NEXT_TBTT1_TIME field)
                                     Unit: TU
                                     The following TBTT and related function will be triggered by this modified timing. This field is only valid when non-zero value in this field is specified; it will not affect the original TBTT calibration or related functions. It will not affect the TBTT value set by SW, either.
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T1SFR_EARLIER_TBTT1_OFFSET_ADDR        BN0_WF_LPON_TOP_T1SFR_ADDR
#define BN0_WF_LPON_TOP_T1SFR_EARLIER_TBTT1_OFFSET_MASK        0x0000FFFF                // EARLIER_TBTT1_OFFSET[15..0]
#define BN0_WF_LPON_TOP_T1SFR_EARLIER_TBTT1_OFFSET_SHFT        0

/* =====================================================================================

  ---T2SFR (0x820EB000 + 0x120)---

    EARLIER_TBTT2_OFFSET[15..0]  - (RW) Time offset to compensate by subtracting original HW calculated TBTT (in NEXT_TBTT2_TIME field)
                                     Unit: TU
                                     The following TBTT and related function will be triggered by this modified timing. This field is only valid when non-zero value in this field is specified; it will not affect the original TBTT calibration or related functions. It will not affect the TBTT value set by SW, either.
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T2SFR_EARLIER_TBTT2_OFFSET_ADDR        BN0_WF_LPON_TOP_T2SFR_ADDR
#define BN0_WF_LPON_TOP_T2SFR_EARLIER_TBTT2_OFFSET_MASK        0x0000FFFF                // EARLIER_TBTT2_OFFSET[15..0]
#define BN0_WF_LPON_TOP_T2SFR_EARLIER_TBTT2_OFFSET_SHFT        0

/* =====================================================================================

  ---T3SFR (0x820EB000 + 0x124)---

    EARLIER_TBTT3_OFFSET[15..0]  - (RW) Time offset to compensate by subtracting original HW calculated TBTT (in NEXT_TBTT3_TIME field)
                                     Unit: TU
                                     The following TBTT and related function will be triggered by this modified timing. This field is only valid when non-zero value in this field is specified; it will not affect the original TBTT calibration or related functions. It will not affect the TBTT value set by SW, either.
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_T3SFR_EARLIER_TBTT3_OFFSET_ADDR        BN0_WF_LPON_TOP_T3SFR_ADDR
#define BN0_WF_LPON_TOP_T3SFR_EARLIER_TBTT3_OFFSET_MASK        0x0000FFFF                // EARLIER_TBTT3_OFFSET[15..0]
#define BN0_WF_LPON_TOP_T3SFR_EARLIER_TBTT3_OFFSET_SHFT        0

/* =====================================================================================

  ---TT0SFR (0x820EB000 + 0x128)---

    EARLIER_TTTT0_OFFSET[23..0]  - (RW) Time offset to compensate by subtracting original HW calculated TTTT (in NEXT_TTTT0_TIME field)
                                     Unit: TU
                                     The following TTTT and related function will be triggered by this modified timing. This field is only valid when non-zero value is specified in this field; it will not affect the original TTTT calibration or related functions. It will not affect the TTTT value set by SW, either.
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT0SFR_EARLIER_TTTT0_OFFSET_ADDR       BN0_WF_LPON_TOP_TT0SFR_ADDR
#define BN0_WF_LPON_TOP_TT0SFR_EARLIER_TTTT0_OFFSET_MASK       0x00FFFFFF                // EARLIER_TTTT0_OFFSET[23..0]
#define BN0_WF_LPON_TOP_TT0SFR_EARLIER_TTTT0_OFFSET_SHFT       0

/* =====================================================================================

  ---TT1SFR (0x820EB000 + 0x12c)---

    EARLIER_TTTT1_OFFSET[23..0]  - (RW) Time offset to compensate by subtracting original HW calculated TTTT (in NEXT_TTTT1_TIME field)
                                     Unit: TU
                                     The following TTTT and related function will be triggered by this modified timing. This field is only valid when non-zero value is specified in this field; it will not affect the original TTTT calibration or related functions. It will not affect the TTTT value set by SW, either.
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT1SFR_EARLIER_TTTT1_OFFSET_ADDR       BN0_WF_LPON_TOP_TT1SFR_ADDR
#define BN0_WF_LPON_TOP_TT1SFR_EARLIER_TTTT1_OFFSET_MASK       0x00FFFFFF                // EARLIER_TTTT1_OFFSET[23..0]
#define BN0_WF_LPON_TOP_TT1SFR_EARLIER_TTTT1_OFFSET_SHFT       0

/* =====================================================================================

  ---TT2SFR (0x820EB000 + 0x130)---

    EARLIER_TTTT2_OFFSET[23..0]  - (RW) Time offset to compensate by subtracting original HW calculated TTTT (in NEXT_TTTT2_TIME field)
                                     Unit: TU
                                     The following TTTT and related function will be triggered by this modified timing. This field is only valid when non-zero value is specified in this field; it will not affect the original TTTT calibration or related functions. It will not affect the TTTT value set by SW, either.
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT2SFR_EARLIER_TTTT2_OFFSET_ADDR       BN0_WF_LPON_TOP_TT2SFR_ADDR
#define BN0_WF_LPON_TOP_TT2SFR_EARLIER_TTTT2_OFFSET_MASK       0x00FFFFFF                // EARLIER_TTTT2_OFFSET[23..0]
#define BN0_WF_LPON_TOP_TT2SFR_EARLIER_TTTT2_OFFSET_SHFT       0

/* =====================================================================================

  ---TT3SFR (0x820EB000 + 0x134)---

    EARLIER_TTTT3_OFFSET[23..0]  - (RW) Time offset to compensate by subtracting original HW calculated TTTT (in NEXT_TTTT3_TIME field)
                                     Unit: TU
                                     The following TTTT and related function will be triggered by this modified timing. This field is only valid when non-zero value is specified in this field; it will not affect the original TTTT calibration or related functions. It will not affect the TTTT value set by SW, either.
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TT3SFR_EARLIER_TTTT3_OFFSET_ADDR       BN0_WF_LPON_TOP_TT3SFR_ADDR
#define BN0_WF_LPON_TOP_TT3SFR_EARLIER_TTTT3_OFFSET_MASK       0x00FFFFFF                // EARLIER_TTTT3_OFFSET[23..0]
#define BN0_WF_LPON_TOP_TT3SFR_EARLIER_TTTT3_OFFSET_SHFT       0

/* =====================================================================================

  ---TTR (0x820EB000 + 0x138)---

    TRAP0_TIME[31..0]            - (RW) Trap time means that when the low 32 bits of one specific TSF timer reaches this value (selected by TXTCR0.TSF_TRAP0_SEL), some events will happen according to the configuration of TXTCR0.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TTR_TRAP0_TIME_ADDR                    BN0_WF_LPON_TOP_TTR_ADDR
#define BN0_WF_LPON_TOP_TTR_TRAP0_TIME_MASK                    0xFFFFFFFF                // TRAP0_TIME[31..0]
#define BN0_WF_LPON_TOP_TTR_TRAP0_TIME_SHFT                    0

/* =====================================================================================

  ---TTR1 (0x820EB000 + 0x13c)---

    TRAP1_TIME[31..0]            - (RW) Same as TRAP0_TIME

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TTR1_TRAP1_TIME_ADDR                   BN0_WF_LPON_TOP_TTR1_ADDR
#define BN0_WF_LPON_TOP_TTR1_TRAP1_TIME_MASK                   0xFFFFFFFF                // TRAP1_TIME[31..0]
#define BN0_WF_LPON_TOP_TTR1_TRAP1_TIME_SHFT                   0

/* =====================================================================================

  ---TTR2 (0x820EB000 + 0x140)---

    TRAP2_TIME[31..0]            - (RW) Same as TRAP0_TIME

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TTR2_TRAP2_TIME_ADDR                   BN0_WF_LPON_TOP_TTR2_ADDR
#define BN0_WF_LPON_TOP_TTR2_TRAP2_TIME_MASK                   0xFFFFFFFF                // TRAP2_TIME[31..0]
#define BN0_WF_LPON_TOP_TTR2_TRAP2_TIME_SHFT                   0

/* =====================================================================================

  ---TTR3 (0x820EB000 + 0x144)---

    TRAP3_TIME[31..0]            - (RW) Same as TRAP0_TIME

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TTR3_TRAP3_TIME_ADDR                   BN0_WF_LPON_TOP_TTR3_ADDR
#define BN0_WF_LPON_TOP_TTR3_TRAP3_TIME_MASK                   0xFFFFFFFF                // TRAP3_TIME[31..0]
#define BN0_WF_LPON_TOP_TTR3_TRAP3_TIME_SHFT                   0

/* =====================================================================================

  ---TTSR (0x820EB000 + 0x148)---

    TSF_TIME_VALUE[21..0]        - (RW) tsf timer count value
                                     Unit: 1us
    RESERVED22[23..22]           - (RO) Reserved bits
    LOCAL_TSF_TIMER_ID[25..24]   - (RW) Controls which tsf(tsf0-3,associated to bssid0-3) to be referenced for the timer.
    RESERVED26[27..26]           - (RO) Reserved bits
    PERIODICAL_CTRL[28]          - (RW) Controls time_value used for T0 timer 
                                     0: Start time
                                     1: Period (If TIME_VALUE is 0 when this value is set, it will be a one-shot timer; otherwise, it will be an auto-repeat timer.)
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TTSR_PERIODICAL_CTRL_ADDR              BN0_WF_LPON_TOP_TTSR_ADDR
#define BN0_WF_LPON_TOP_TTSR_PERIODICAL_CTRL_MASK              0x10000000                // PERIODICAL_CTRL[28]
#define BN0_WF_LPON_TOP_TTSR_PERIODICAL_CTRL_SHFT              28
#define BN0_WF_LPON_TOP_TTSR_LOCAL_TSF_TIMER_ID_ADDR           BN0_WF_LPON_TOP_TTSR_ADDR
#define BN0_WF_LPON_TOP_TTSR_LOCAL_TSF_TIMER_ID_MASK           0x03000000                // LOCAL_TSF_TIMER_ID[25..24]
#define BN0_WF_LPON_TOP_TTSR_LOCAL_TSF_TIMER_ID_SHFT           24
#define BN0_WF_LPON_TOP_TTSR_TSF_TIME_VALUE_ADDR               BN0_WF_LPON_TOP_TTSR_ADDR
#define BN0_WF_LPON_TOP_TTSR_TSF_TIME_VALUE_MASK               0x003FFFFF                // TSF_TIME_VALUE[21..0]
#define BN0_WF_LPON_TOP_TTSR_TSF_TIME_VALUE_SHFT               0

/* =====================================================================================

  ---TTSR1 (0x820EB000 + 0x14c)---

    TSF_TIME_VALUE[21..0]        - (RW) tsf timer count value
                                     Unit: 1us
    RESERVED22[23..22]           - (RO) Reserved bits
    LOCAL_TSF_TIMER_ID[25..24]   - (RW) Controls which tsf(tsf0-3,associated to bssid0-3) to be referenced for the timer.
    RESERVED26[27..26]           - (RO) Reserved bits
    PERIODICAL_CTRL[28]          - (RW) Controls time_value used for T1 timer 
                                     0: Start time
                                     1: Period (If TIME_VALUE is 0 when this value is set, it will be a one-shot timer; otherwise, it will be an auto-repeat timer.)
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TTSR1_PERIODICAL_CTRL_ADDR             BN0_WF_LPON_TOP_TTSR1_ADDR
#define BN0_WF_LPON_TOP_TTSR1_PERIODICAL_CTRL_MASK             0x10000000                // PERIODICAL_CTRL[28]
#define BN0_WF_LPON_TOP_TTSR1_PERIODICAL_CTRL_SHFT             28
#define BN0_WF_LPON_TOP_TTSR1_LOCAL_TSF_TIMER_ID_ADDR          BN0_WF_LPON_TOP_TTSR1_ADDR
#define BN0_WF_LPON_TOP_TTSR1_LOCAL_TSF_TIMER_ID_MASK          0x03000000                // LOCAL_TSF_TIMER_ID[25..24]
#define BN0_WF_LPON_TOP_TTSR1_LOCAL_TSF_TIMER_ID_SHFT          24
#define BN0_WF_LPON_TOP_TTSR1_TSF_TIME_VALUE_ADDR              BN0_WF_LPON_TOP_TTSR1_ADDR
#define BN0_WF_LPON_TOP_TTSR1_TSF_TIME_VALUE_MASK              0x003FFFFF                // TSF_TIME_VALUE[21..0]
#define BN0_WF_LPON_TOP_TTSR1_TSF_TIME_VALUE_SHFT              0

/* =====================================================================================

  ---TTSR2 (0x820EB000 + 0x150)---

    TSF_TIME_VALUE[21..0]        - (RW) tsf timer count value
                                     Unit: 1us
    RESERVED22[23..22]           - (RO) Reserved bits
    LOCAL_TSF_TIMER_ID[25..24]   - (RW) Controls which tsf(tsf0-3,associated to bssid0-3) to be referenced for the timer.
    RESERVED26[27..26]           - (RO) Reserved bits
    PERIODICAL_CTRL[28]          - (RW) Controls time_value used for T2 timer 
                                     0: Start time
                                     1: Period (If TIME_VALUE is 0 when this value is set, it will be a one-shot timer; otherwise, it will be an auto-repeat timer.)
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TTSR2_PERIODICAL_CTRL_ADDR             BN0_WF_LPON_TOP_TTSR2_ADDR
#define BN0_WF_LPON_TOP_TTSR2_PERIODICAL_CTRL_MASK             0x10000000                // PERIODICAL_CTRL[28]
#define BN0_WF_LPON_TOP_TTSR2_PERIODICAL_CTRL_SHFT             28
#define BN0_WF_LPON_TOP_TTSR2_LOCAL_TSF_TIMER_ID_ADDR          BN0_WF_LPON_TOP_TTSR2_ADDR
#define BN0_WF_LPON_TOP_TTSR2_LOCAL_TSF_TIMER_ID_MASK          0x03000000                // LOCAL_TSF_TIMER_ID[25..24]
#define BN0_WF_LPON_TOP_TTSR2_LOCAL_TSF_TIMER_ID_SHFT          24
#define BN0_WF_LPON_TOP_TTSR2_TSF_TIME_VALUE_ADDR              BN0_WF_LPON_TOP_TTSR2_ADDR
#define BN0_WF_LPON_TOP_TTSR2_TSF_TIME_VALUE_MASK              0x003FFFFF                // TSF_TIME_VALUE[21..0]
#define BN0_WF_LPON_TOP_TTSR2_TSF_TIME_VALUE_SHFT              0

/* =====================================================================================

  ---TTSR3 (0x820EB000 + 0x154)---

    TSF_TIME_VALUE[21..0]        - (RW) tsf timer count value
                                     Unit: 1us
    RESERVED22[23..22]           - (RO) Reserved bits
    LOCAL_TSF_TIMER_ID[25..24]   - (RW) Controls which tsf(tsf0-3,associated to bssid0-3) to be referenced for the timer.
    RESERVED26[27..26]           - (RO) Reserved bits
    PERIODICAL_CTRL[28]          - (RW) Controls time_value used for T3 timer 
                                     0: Start time
                                     1: Period (If TIME_VALUE is 0 when this value is set, it will be a one-shot timer; otherwise, it will be an auto-repeat timer.)
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TTSR3_PERIODICAL_CTRL_ADDR             BN0_WF_LPON_TOP_TTSR3_ADDR
#define BN0_WF_LPON_TOP_TTSR3_PERIODICAL_CTRL_MASK             0x10000000                // PERIODICAL_CTRL[28]
#define BN0_WF_LPON_TOP_TTSR3_PERIODICAL_CTRL_SHFT             28
#define BN0_WF_LPON_TOP_TTSR3_LOCAL_TSF_TIMER_ID_ADDR          BN0_WF_LPON_TOP_TTSR3_ADDR
#define BN0_WF_LPON_TOP_TTSR3_LOCAL_TSF_TIMER_ID_MASK          0x03000000                // LOCAL_TSF_TIMER_ID[25..24]
#define BN0_WF_LPON_TOP_TTSR3_LOCAL_TSF_TIMER_ID_SHFT          24
#define BN0_WF_LPON_TOP_TTSR3_TSF_TIME_VALUE_ADDR              BN0_WF_LPON_TOP_TTSR3_ADDR
#define BN0_WF_LPON_TOP_TTSR3_TSF_TIME_VALUE_MASK              0x003FFFFF                // TSF_TIME_VALUE[21..0]
#define BN0_WF_LPON_TOP_TTSR3_TSF_TIME_VALUE_SHFT              0

/* =====================================================================================

  ---TTTR0 (0x820EB000 + 0x158)---

    LP_TAR_TSF_TIMER0[21..0]     - (RW) HW local TSF timer 0 target value
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED22[31..22]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TTTR0_LP_TAR_TSF_TIMER0_ADDR           BN0_WF_LPON_TOP_TTTR0_ADDR
#define BN0_WF_LPON_TOP_TTTR0_LP_TAR_TSF_TIMER0_MASK           0x003FFFFF                // LP_TAR_TSF_TIMER0[21..0]
#define BN0_WF_LPON_TOP_TTTR0_LP_TAR_TSF_TIMER0_SHFT           0

/* =====================================================================================

  ---TTTR1 (0x820EB000 + 0x15c)---

    LP_TAR_TSF_TIMER1[21..0]     - (RW) HW local TSF timer 1 target value
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED22[31..22]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TTTR1_LP_TAR_TSF_TIMER1_ADDR           BN0_WF_LPON_TOP_TTTR1_ADDR
#define BN0_WF_LPON_TOP_TTTR1_LP_TAR_TSF_TIMER1_MASK           0x003FFFFF                // LP_TAR_TSF_TIMER1[21..0]
#define BN0_WF_LPON_TOP_TTTR1_LP_TAR_TSF_TIMER1_SHFT           0

/* =====================================================================================

  ---TTTR2 (0x820EB000 + 0x160)---

    LP_TAR_TSF_TIMER2[21..0]     - (RW) HW local TSF timer 2 target value
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED22[31..22]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TTTR2_LP_TAR_TSF_TIMER2_ADDR           BN0_WF_LPON_TOP_TTTR2_ADDR
#define BN0_WF_LPON_TOP_TTTR2_LP_TAR_TSF_TIMER2_MASK           0x003FFFFF                // LP_TAR_TSF_TIMER2[21..0]
#define BN0_WF_LPON_TOP_TTTR2_LP_TAR_TSF_TIMER2_SHFT           0

/* =====================================================================================

  ---TTTR3 (0x820EB000 + 0x164)---

    LP_TAR_TSF_TIMER3[21..0]     - (RW) HW local TSF timer 3 target value
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED22[31..22]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TTTR3_LP_TAR_TSF_TIMER3_ADDR           BN0_WF_LPON_TOP_TTTR3_ADDR
#define BN0_WF_LPON_TOP_TTTR3_LP_TAR_TSF_TIMER3_MASK           0x003FFFFF                // LP_TAR_TSF_TIMER3[21..0]
#define BN0_WF_LPON_TOP_TTTR3_LP_TAR_TSF_TIMER3_SHFT           0

/* =====================================================================================

  ---TFRSR (0x820EB000 + 0x168)---

    T8_FREE_TIME_VALUE[25..0]    - (RW) T8 free-run timer count value
                                     Unit: 1us
    RESERVED26[30..26]           - (RO) Reserved bits
    T8_PERIODICAL_CTRL[31]       - (RW) Enables T8 timer auto-reload function which can work as a periodical timer
                                     Otherwise, it will be single-shot timer.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TFRSR_T8_PERIODICAL_CTRL_ADDR          BN0_WF_LPON_TOP_TFRSR_ADDR
#define BN0_WF_LPON_TOP_TFRSR_T8_PERIODICAL_CTRL_MASK          0x80000000                // T8_PERIODICAL_CTRL[31]
#define BN0_WF_LPON_TOP_TFRSR_T8_PERIODICAL_CTRL_SHFT          31
#define BN0_WF_LPON_TOP_TFRSR_T8_FREE_TIME_VALUE_ADDR          BN0_WF_LPON_TOP_TFRSR_ADDR
#define BN0_WF_LPON_TOP_TFRSR_T8_FREE_TIME_VALUE_MASK          0x03FFFFFF                // T8_FREE_TIME_VALUE[25..0]
#define BN0_WF_LPON_TOP_TFRSR_T8_FREE_TIME_VALUE_SHFT          0

/* =====================================================================================

  ---TGTR (0x820EB000 + 0x16c)---

    LP_TAR_GTIMER[25..0]         - (RW) HW local general timer target value
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TGTR_LP_TAR_GTIMER_ADDR                BN0_WF_LPON_TOP_TGTR_ADDR
#define BN0_WF_LPON_TOP_TGTR_LP_TAR_GTIMER_MASK                0x03FFFFFF                // LP_TAR_GTIMER[25..0]
#define BN0_WF_LPON_TOP_TGTR_LP_TAR_GTIMER_SHFT                0

/* =====================================================================================

  ---TICKER0 (0x820EB000 + 0x170)---

    TICKER0_L[31..0]             - (RU) DTIM COMPENSATE TICKER 0_L

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TICKER0_TICKER0_L_ADDR                 BN0_WF_LPON_TOP_TICKER0_ADDR
#define BN0_WF_LPON_TOP_TICKER0_TICKER0_L_MASK                 0xFFFFFFFF                // TICKER0_L[31..0]
#define BN0_WF_LPON_TOP_TICKER0_TICKER0_L_SHFT                 0

/* =====================================================================================

  ---TICKER1 (0x820EB000 + 0x174)---

    TICKER1_L[31..0]             - (RU) DTIM COMPENSATE TICKER 1_L

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TICKER1_TICKER1_L_ADDR                 BN0_WF_LPON_TOP_TICKER1_ADDR
#define BN0_WF_LPON_TOP_TICKER1_TICKER1_L_MASK                 0xFFFFFFFF                // TICKER1_L[31..0]
#define BN0_WF_LPON_TOP_TICKER1_TICKER1_L_SHFT                 0

/* =====================================================================================

  ---TICKER2 (0x820EB000 + 0x178)---

    TICKER2_L[31..0]             - (RU) DTIM COMPENSATE TICKER 2_L

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TICKER2_TICKER2_L_ADDR                 BN0_WF_LPON_TOP_TICKER2_ADDR
#define BN0_WF_LPON_TOP_TICKER2_TICKER2_L_MASK                 0xFFFFFFFF                // TICKER2_L[31..0]
#define BN0_WF_LPON_TOP_TICKER2_TICKER2_L_SHFT                 0

/* =====================================================================================

  ---TICKER3 (0x820EB000 + 0x17c)---

    TICKER3_L[31..0]             - (RU) DTIM COMPENSATE TICKER 3_L

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TICKER3_TICKER3_L_ADDR                 BN0_WF_LPON_TOP_TICKER3_ADDR
#define BN0_WF_LPON_TOP_TICKER3_TICKER3_L_MASK                 0xFFFFFFFF                // TICKER3_L[31..0]
#define BN0_WF_LPON_TOP_TICKER3_TICKER3_L_SHFT                 0

/* =====================================================================================

  ---TICKER4 (0x820EB000 + 0x180)---

    TICKER4_L[31..0]             - (RU) TBTT COMPENSATE TICKER 0_L

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TICKER4_TICKER4_L_ADDR                 BN0_WF_LPON_TOP_TICKER4_ADDR
#define BN0_WF_LPON_TOP_TICKER4_TICKER4_L_MASK                 0xFFFFFFFF                // TICKER4_L[31..0]
#define BN0_WF_LPON_TOP_TICKER4_TICKER4_L_SHFT                 0

/* =====================================================================================

  ---TICKER5 (0x820EB000 + 0x184)---

    TICKER5_L[31..0]             - (RU) TBTT COMPENSATE TICKER 1_L

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TICKER5_TICKER5_L_ADDR                 BN0_WF_LPON_TOP_TICKER5_ADDR
#define BN0_WF_LPON_TOP_TICKER5_TICKER5_L_MASK                 0xFFFFFFFF                // TICKER5_L[31..0]
#define BN0_WF_LPON_TOP_TICKER5_TICKER5_L_SHFT                 0

/* =====================================================================================

  ---TICKER6 (0x820EB000 + 0x188)---

    TICKER6_L[31..0]             - (RU) TBTT COMPENSATE TICKER 2_L

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TICKER6_TICKER6_L_ADDR                 BN0_WF_LPON_TOP_TICKER6_ADDR
#define BN0_WF_LPON_TOP_TICKER6_TICKER6_L_MASK                 0xFFFFFFFF                // TICKER6_L[31..0]
#define BN0_WF_LPON_TOP_TICKER6_TICKER6_L_SHFT                 0

/* =====================================================================================

  ---TICKER7 (0x820EB000 + 0x18c)---

    TICKER7_L[31..0]             - (RU) TBTT COMPENSATE TICKER 3_L

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TICKER7_TICKER7_L_ADDR                 BN0_WF_LPON_TOP_TICKER7_ADDR
#define BN0_WF_LPON_TOP_TICKER7_TICKER7_L_MASK                 0xFFFFFFFF                // TICKER7_L[31..0]
#define BN0_WF_LPON_TOP_TICKER7_TICKER7_L_SHFT                 0

/* =====================================================================================

  ---TICKER8 (0x820EB000 + 0x190)---

    TICKER0_H[3..0]              - (RU) DTIM COMPENSATE TICKER 0_H
    RESERVED4[7..4]              - (RO) Reserved bits
    TICKER1_H[11..8]             - (RU) DTIM COMPENSATE TICKER 1_H
    RESERVED12[15..12]           - (RO) Reserved bits
    TICKER2_H[19..16]            - (RU) DTIM COMPENSATE TICKER 2_H
    RESERVED20[23..20]           - (RO) Reserved bits
    TICKER3_H[27..24]            - (RU) DTIM COMPENSATE TICKER 3_H
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TICKER8_TICKER3_H_ADDR                 BN0_WF_LPON_TOP_TICKER8_ADDR
#define BN0_WF_LPON_TOP_TICKER8_TICKER3_H_MASK                 0x0F000000                // TICKER3_H[27..24]
#define BN0_WF_LPON_TOP_TICKER8_TICKER3_H_SHFT                 24
#define BN0_WF_LPON_TOP_TICKER8_TICKER2_H_ADDR                 BN0_WF_LPON_TOP_TICKER8_ADDR
#define BN0_WF_LPON_TOP_TICKER8_TICKER2_H_MASK                 0x000F0000                // TICKER2_H[19..16]
#define BN0_WF_LPON_TOP_TICKER8_TICKER2_H_SHFT                 16
#define BN0_WF_LPON_TOP_TICKER8_TICKER1_H_ADDR                 BN0_WF_LPON_TOP_TICKER8_ADDR
#define BN0_WF_LPON_TOP_TICKER8_TICKER1_H_MASK                 0x00000F00                // TICKER1_H[11..8]
#define BN0_WF_LPON_TOP_TICKER8_TICKER1_H_SHFT                 8
#define BN0_WF_LPON_TOP_TICKER8_TICKER0_H_ADDR                 BN0_WF_LPON_TOP_TICKER8_ADDR
#define BN0_WF_LPON_TOP_TICKER8_TICKER0_H_MASK                 0x0000000F                // TICKER0_H[3..0]
#define BN0_WF_LPON_TOP_TICKER8_TICKER0_H_SHFT                 0

/* =====================================================================================

  ---TICKER9 (0x820EB000 + 0x194)---

    TICKER4_H[3..0]              - (RU) TBTT COMPENSATE TICKER 0_H
    RESERVED4[7..4]              - (RO) Reserved bits
    TICKER5_H[11..8]             - (RU) TBTT COMPENSATE TICKER 1_H
    RESERVED12[15..12]           - (RO) Reserved bits
    TICKER6_H[19..16]            - (RU) TBTT COMPENSATE TICKER 2_H
    RESERVED20[23..20]           - (RO) Reserved bits
    TICKER7_H[27..24]            - (RU) TBTT COMPENSATE TICKER 3_H
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TICKER9_TICKER7_H_ADDR                 BN0_WF_LPON_TOP_TICKER9_ADDR
#define BN0_WF_LPON_TOP_TICKER9_TICKER7_H_MASK                 0x0F000000                // TICKER7_H[27..24]
#define BN0_WF_LPON_TOP_TICKER9_TICKER7_H_SHFT                 24
#define BN0_WF_LPON_TOP_TICKER9_TICKER6_H_ADDR                 BN0_WF_LPON_TOP_TICKER9_ADDR
#define BN0_WF_LPON_TOP_TICKER9_TICKER6_H_MASK                 0x000F0000                // TICKER6_H[19..16]
#define BN0_WF_LPON_TOP_TICKER9_TICKER6_H_SHFT                 16
#define BN0_WF_LPON_TOP_TICKER9_TICKER5_H_ADDR                 BN0_WF_LPON_TOP_TICKER9_ADDR
#define BN0_WF_LPON_TOP_TICKER9_TICKER5_H_MASK                 0x00000F00                // TICKER5_H[11..8]
#define BN0_WF_LPON_TOP_TICKER9_TICKER5_H_SHFT                 8
#define BN0_WF_LPON_TOP_TICKER9_TICKER4_H_ADDR                 BN0_WF_LPON_TOP_TICKER9_ADDR
#define BN0_WF_LPON_TOP_TICKER9_TICKER4_H_MASK                 0x0000000F                // TICKER4_H[3..0]
#define BN0_WF_LPON_TOP_TICKER9_TICKER4_H_SHFT                 0

/* =====================================================================================

  ---PISR (0x820EB000 + 0x198)---

    PRETBTT_INTERVAL0[7..0]      - (RW) Same as PRETBTT_INTERVAL3
    PRETBTT_INTERVAL1[15..8]     - (RW) Same as PRETBTT_INTERVAL3
    PRETBTT_INTERVAL2[23..16]    - (RW) Same as PRETBTT_INTERVAL3
    PRETBTT_INTERVAL3[31..24]    - (RW) Period in unit of 64us before TBTT for preTBTT or preDTIM interrupt generation
                                     If this value is not equal to 0, MAC will wake up earlier with this offset than in the case it equals 0.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_PISR_PRETBTT_INTERVAL3_ADDR            BN0_WF_LPON_TOP_PISR_ADDR
#define BN0_WF_LPON_TOP_PISR_PRETBTT_INTERVAL3_MASK            0xFF000000                // PRETBTT_INTERVAL3[31..24]
#define BN0_WF_LPON_TOP_PISR_PRETBTT_INTERVAL3_SHFT            24
#define BN0_WF_LPON_TOP_PISR_PRETBTT_INTERVAL2_ADDR            BN0_WF_LPON_TOP_PISR_ADDR
#define BN0_WF_LPON_TOP_PISR_PRETBTT_INTERVAL2_MASK            0x00FF0000                // PRETBTT_INTERVAL2[23..16]
#define BN0_WF_LPON_TOP_PISR_PRETBTT_INTERVAL2_SHFT            16
#define BN0_WF_LPON_TOP_PISR_PRETBTT_INTERVAL1_ADDR            BN0_WF_LPON_TOP_PISR_ADDR
#define BN0_WF_LPON_TOP_PISR_PRETBTT_INTERVAL1_MASK            0x0000FF00                // PRETBTT_INTERVAL1[15..8]
#define BN0_WF_LPON_TOP_PISR_PRETBTT_INTERVAL1_SHFT            8
#define BN0_WF_LPON_TOP_PISR_PRETBTT_INTERVAL0_ADDR            BN0_WF_LPON_TOP_PISR_ADDR
#define BN0_WF_LPON_TOP_PISR_PRETBTT_INTERVAL0_MASK            0x000000FF                // PRETBTT_INTERVAL0[7..0]
#define BN0_WF_LPON_TOP_PISR_PRETBTT_INTERVAL0_SHFT            0

/* =====================================================================================

  ---PTTISR (0x820EB000 + 0x19c)---

    PRETTTT_INTERVAL0[7..0]      - (RW) Same as PRETTTT_INTERVAL3
    PRETTTT_INTERVAL1[15..8]     - (RW) Same as PRETTTT_INTERVAL3
    PRETTTT_INTERVAL2[23..16]    - (RW) Same as PRETTTT_INTERVAL3
    PRETTTT_INTERVAL3[31..24]    - (RW) This period in unit of 64us before TTTT for preTTTT interrupt generation
                                     If this value is not equal to 0, MAC will wake up earlier with this offset than in the case it equals 0.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_PTTISR_PRETTTT_INTERVAL3_ADDR          BN0_WF_LPON_TOP_PTTISR_ADDR
#define BN0_WF_LPON_TOP_PTTISR_PRETTTT_INTERVAL3_MASK          0xFF000000                // PRETTTT_INTERVAL3[31..24]
#define BN0_WF_LPON_TOP_PTTISR_PRETTTT_INTERVAL3_SHFT          24
#define BN0_WF_LPON_TOP_PTTISR_PRETTTT_INTERVAL2_ADDR          BN0_WF_LPON_TOP_PTTISR_ADDR
#define BN0_WF_LPON_TOP_PTTISR_PRETTTT_INTERVAL2_MASK          0x00FF0000                // PRETTTT_INTERVAL2[23..16]
#define BN0_WF_LPON_TOP_PTTISR_PRETTTT_INTERVAL2_SHFT          16
#define BN0_WF_LPON_TOP_PTTISR_PRETTTT_INTERVAL1_ADDR          BN0_WF_LPON_TOP_PTTISR_ADDR
#define BN0_WF_LPON_TOP_PTTISR_PRETTTT_INTERVAL1_MASK          0x0000FF00                // PRETTTT_INTERVAL1[15..8]
#define BN0_WF_LPON_TOP_PTTISR_PRETTTT_INTERVAL1_SHFT          8
#define BN0_WF_LPON_TOP_PTTISR_PRETTTT_INTERVAL0_ADDR          BN0_WF_LPON_TOP_PTTISR_ADDR
#define BN0_WF_LPON_TOP_PTTISR_PRETTTT_INTERVAL0_MASK          0x000000FF                // PRETTTT_INTERVAL0[7..0]
#define BN0_WF_LPON_TOP_PTTISR_PRETTTT_INTERVAL0_SHFT          0

/* =====================================================================================

  ---BTEIR (0x820EB000 + 0x1a0)---

    BCN_EARLIER_INTERVAL[7..0]   - (RU) Detected max. interval (unit: 2us) when the situation of normal TSF in Beacon is met and Beacon is sent out earlier than TBTT
                                     When BEIR.BEI_cal_en is asserted, this value will be first reset to 0 then updated by the detected max. interval.
                                     Nominally Beacon should be sent out after TBTT and its interval will be 0. SW can use this value to know if Beacon can be sent out earlier than TBTT and add it to LPPTCR. OSC_STABLE_TIME to avoid Beacon loss.
    BEI_CAL_EN[8]                - (RW) Enables calculation for BEIR.BCN_Earlier_Interval from the 1st signal of Beacon (from BSSID 0,1,2 or 3) to corresponding TBTT (0,1,2 or 3) when the situation of normal TSF in Beacon is met and Beacon is sent out earlier than TBTT
    RESERVED9[15..9]             - (RO) Reserved bits
    TIM_EARLIER_INTERVAL[23..16] - (RU) Detected max. interval (unit: 2us) when the situation of normal TSF in BTIM is met and BTIM is sent out earlier than TTTT
                                     When TEIR.TEI_cal_en is asserted, this value will be first reset to 0  then updated by the detected max. interval.
                                     Nominally Beacon should be sent out after TTTT and its interval will be 0. SW can use this value to know if BTIM can be sent out earlier than TTTT and add it to LPPTCR. OSC_STABLE_TIME to avoid Beacon loss.
    TEI_CAL_EN[24]               - (RW) Enables calculation for TEIR.TIM_Earlier_Interval from the 1st signal of Beacon (from BSSID 0,1,2 or 3) to corresponding TTTT (0,1,2 or 3) when the situation of normal TSF in BTIM is met and BTIM is sent out earlier than TTTT.
    BTEI_TSF_SRC_SEL[25]         - (RW) Indicates TSF count value used to calculate early interval
                                     0: TSF timestamp parsed by RMAC
                                     1: LMAC local TSF count
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_BTEIR_BTEI_TSF_SRC_SEL_ADDR            BN0_WF_LPON_TOP_BTEIR_ADDR
#define BN0_WF_LPON_TOP_BTEIR_BTEI_TSF_SRC_SEL_MASK            0x02000000                // BTEI_TSF_SRC_SEL[25]
#define BN0_WF_LPON_TOP_BTEIR_BTEI_TSF_SRC_SEL_SHFT            25
#define BN0_WF_LPON_TOP_BTEIR_TEI_CAL_EN_ADDR                  BN0_WF_LPON_TOP_BTEIR_ADDR
#define BN0_WF_LPON_TOP_BTEIR_TEI_CAL_EN_MASK                  0x01000000                // TEI_CAL_EN[24]
#define BN0_WF_LPON_TOP_BTEIR_TEI_CAL_EN_SHFT                  24
#define BN0_WF_LPON_TOP_BTEIR_TIM_EARLIER_INTERVAL_ADDR        BN0_WF_LPON_TOP_BTEIR_ADDR
#define BN0_WF_LPON_TOP_BTEIR_TIM_EARLIER_INTERVAL_MASK        0x00FF0000                // TIM_EARLIER_INTERVAL[23..16]
#define BN0_WF_LPON_TOP_BTEIR_TIM_EARLIER_INTERVAL_SHFT        16
#define BN0_WF_LPON_TOP_BTEIR_BEI_CAL_EN_ADDR                  BN0_WF_LPON_TOP_BTEIR_ADDR
#define BN0_WF_LPON_TOP_BTEIR_BEI_CAL_EN_MASK                  0x00000100                // BEI_CAL_EN[8]
#define BN0_WF_LPON_TOP_BTEIR_BEI_CAL_EN_SHFT                  8
#define BN0_WF_LPON_TOP_BTEIR_BCN_EARLIER_INTERVAL_ADDR        BN0_WF_LPON_TOP_BTEIR_ADDR
#define BN0_WF_LPON_TOP_BTEIR_BCN_EARLIER_INTERVAL_MASK        0x000000FF                // BCN_EARLIER_INTERVAL[7..0]
#define BN0_WF_LPON_TOP_BTEIR_BCN_EARLIER_INTERVAL_SHFT        0

/* =====================================================================================

  ---TIMTR (0x820EB000 + 0x1a4)---

    TIM_BMC_MIN_TIME_LIMIT[5..0] - (RW) Min. time for TIM BMC timeout
                                     Unit: TU
                                     If there is any CCA (or mdrdy, by TCLCR. MIN_TIME_CTRL setting), txpe will occur and the local timeout counter will be reset.
    TIM_BMC_MIN_TIME_LIMIT_VALID[6] - (RW) Indicates validation of TIM_BMC_min_time_limit
                                     If both BMC_max_time_limit_valid and TIM_BMC_min_time_limit_valid are 0, timeout will occur immediately.
    TIM_BMC_MAX_TIME_LIMIT_VALID[7] - (RW) Indicates validation of TIM_BMC_max_time_limit
                                     If both TIM_BMC_max_time_limit_valid and TIM_BMC_min_time_limit_valid are 0, timeout will occur immediately.
    TIM_BMC_MAX_TIME_LIMIT[15..8] - (RW) Max. time for TIM BMC timeout counter last
                                     Unit: 4TU
    TIM_MIN_TIME_LIMIT[21..16]   - (RW) Min. time for beacon timeout
                                     Unit: TU
                                     If there is any CCA (or mdrdy, by TCLCR. MIN_TIME_CTRL setting), txpe will occur and the local timeout counter will be reset.
    TIM_MIN_TIME_LIMIT_VALID[22] - (RW) Indicates validation of min_time_limit
                                     If both tim_max_time_limit_valid and tim_min_time_limit_valid are 0, timeout will occur immediately.
    TIM_MAX_TIME_LIMIT_VALID[23] - (RW) Indicates validation of tim_max_time_limit
                                     If both tim_max_time_limit_valid and tim_min_time_limit_valid are 0, timeout will occur immediately.
    TIM_MAX_TIME_LIMIT[31..24]   - (RW) Max. time for TIM timeout
                                     Unit: 4TU

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TIMTR_TIM_MAX_TIME_LIMIT_ADDR          BN0_WF_LPON_TOP_TIMTR_ADDR
#define BN0_WF_LPON_TOP_TIMTR_TIM_MAX_TIME_LIMIT_MASK          0xFF000000                // TIM_MAX_TIME_LIMIT[31..24]
#define BN0_WF_LPON_TOP_TIMTR_TIM_MAX_TIME_LIMIT_SHFT          24
#define BN0_WF_LPON_TOP_TIMTR_TIM_MAX_TIME_LIMIT_VALID_ADDR    BN0_WF_LPON_TOP_TIMTR_ADDR
#define BN0_WF_LPON_TOP_TIMTR_TIM_MAX_TIME_LIMIT_VALID_MASK    0x00800000                // TIM_MAX_TIME_LIMIT_VALID[23]
#define BN0_WF_LPON_TOP_TIMTR_TIM_MAX_TIME_LIMIT_VALID_SHFT    23
#define BN0_WF_LPON_TOP_TIMTR_TIM_MIN_TIME_LIMIT_VALID_ADDR    BN0_WF_LPON_TOP_TIMTR_ADDR
#define BN0_WF_LPON_TOP_TIMTR_TIM_MIN_TIME_LIMIT_VALID_MASK    0x00400000                // TIM_MIN_TIME_LIMIT_VALID[22]
#define BN0_WF_LPON_TOP_TIMTR_TIM_MIN_TIME_LIMIT_VALID_SHFT    22
#define BN0_WF_LPON_TOP_TIMTR_TIM_MIN_TIME_LIMIT_ADDR          BN0_WF_LPON_TOP_TIMTR_ADDR
#define BN0_WF_LPON_TOP_TIMTR_TIM_MIN_TIME_LIMIT_MASK          0x003F0000                // TIM_MIN_TIME_LIMIT[21..16]
#define BN0_WF_LPON_TOP_TIMTR_TIM_MIN_TIME_LIMIT_SHFT          16
#define BN0_WF_LPON_TOP_TIMTR_TIM_BMC_MAX_TIME_LIMIT_ADDR      BN0_WF_LPON_TOP_TIMTR_ADDR
#define BN0_WF_LPON_TOP_TIMTR_TIM_BMC_MAX_TIME_LIMIT_MASK      0x0000FF00                // TIM_BMC_MAX_TIME_LIMIT[15..8]
#define BN0_WF_LPON_TOP_TIMTR_TIM_BMC_MAX_TIME_LIMIT_SHFT      8
#define BN0_WF_LPON_TOP_TIMTR_TIM_BMC_MAX_TIME_LIMIT_VALID_ADDR BN0_WF_LPON_TOP_TIMTR_ADDR
#define BN0_WF_LPON_TOP_TIMTR_TIM_BMC_MAX_TIME_LIMIT_VALID_MASK 0x00000080                // TIM_BMC_MAX_TIME_LIMIT_VALID[7]
#define BN0_WF_LPON_TOP_TIMTR_TIM_BMC_MAX_TIME_LIMIT_VALID_SHFT 7
#define BN0_WF_LPON_TOP_TIMTR_TIM_BMC_MIN_TIME_LIMIT_VALID_ADDR BN0_WF_LPON_TOP_TIMTR_ADDR
#define BN0_WF_LPON_TOP_TIMTR_TIM_BMC_MIN_TIME_LIMIT_VALID_MASK 0x00000040                // TIM_BMC_MIN_TIME_LIMIT_VALID[6]
#define BN0_WF_LPON_TOP_TIMTR_TIM_BMC_MIN_TIME_LIMIT_VALID_SHFT 6
#define BN0_WF_LPON_TOP_TIMTR_TIM_BMC_MIN_TIME_LIMIT_ADDR      BN0_WF_LPON_TOP_TIMTR_ADDR
#define BN0_WF_LPON_TOP_TIMTR_TIM_BMC_MIN_TIME_LIMIT_MASK      0x0000003F                // TIM_BMC_MIN_TIME_LIMIT[5..0]
#define BN0_WF_LPON_TOP_TIMTR_TIM_BMC_MIN_TIME_LIMIT_SHFT      0

/* =====================================================================================

  ---SPCR (0x820EB000 + 0x1a8)---

    BEACON_SP0_ENABLE[0]         - (RW) 0: Disable and clear beacon service period for BSSID 0 with invaliding beacon timeout event
                                     1: Enable the beacon service period function for BSSID 0. Beacon_SP start/stop condition is shown in the following table.
    BMC_SP0_ENABLE[1]            - (RW) 0: Disable and clear BMC service period for BSSID 0 with invaliding BMC timeout event
                                     1: Enable the BMC service period function for BSSID 0. BMC_SP start/stop condition is shown in the following table.
    BEACON_SP1_ENABLE[2]         - (RW) 0: Disable and clear beacon service period for BSSID 1 with invaliding beacon timeout event
                                     1: Enable the beacon service period function for BSSID 1. Beacon_SP start/stop condition is shown in the following table.
    BMC_SP1_ENABLE[3]            - (RW) 0: Disable and clear BMC service period for BSSID 1with invaliding BMC timeout event
                                     1: Enable BMC service period function for BSSID 1. BMC_SP start/stop condition is shown in the following table.
    BEACON_SP0_RESET[4]          - (WO) Write:
                                     0: No meaning
                                     1: Reset/Clear corresponding service period
    BMC_SP0_RESET[5]             - (WO) Write:
                                     0: No meaning
                                     1: Reset/Clear corresponding service period
    BEACON_SP1_RESET[6]          - (WO) Write:
                                     0: No meaning
                                     1: Reset/Cclear corresponding service period
    BMC_SP1_RESET[7]             - (WO) Write:
                                     0: No meaning
                                     1: Reset/Clear corresponding service period
    BEACON_SP0[8]                - (RU) Reflects the current service period state for BSSID 0
    BMC_SP0[9]                   - (RU) Reflects the current service period state for BSSID 0
    BEACON_SP1[10]               - (RU) Reflects the current service period state for BSSID 1
    BMC_SP1[11]                  - (RU) Reflects the current service period state for BSSID 1
    TBTT0_RFON_SP_ENABLE[12]     - (RW) 0: Disable and clear TBTT RF service period for BSSID 0 with invaliding Green AP mode.
                                     1: Enable the TBTT RF service period function for BSSID 0 with validing Green AP mode.
    TBTT1_RFON_SP_ENABLE[13]     - (RW) 0: Disable and clear TBTT RF service period for BSSID 1 with invaliding Green AP mode.
                                     1: Enable the TBTT RF service period function for BSSID 1 with validing Green AP mode.
    RESERVED14[15..14]           - (RO) Reserved bits
    BEACON_SP2_ENABLE[16]        - (RW) 0: Disable and clear beacon service period for BSSID 2 with invaliding beacon timeout event
                                     1: Enable beacon service period function for BSSID 2. Beacon_SP start/stop condition is shown in the following table.
    BMC_SP2_ENABLE[17]           - (RW) 0: Disable and clear BMC service period for BSSID 2 with invaliding BMC timeout event
                                     1: Enable BMC service period function for BSSID 2. BMC_SP start/stop condition is shown in the following table.
    BEACON_SP3_ENABLE[18]        - (RW) 0: Disable and clear beacon service period for BSSID 3 with invaliding beacon timeout event
                                     1: Enable beacon service period function for BSSID 3. Beacon_SP start/stop condition is shown in the following table.
    BMC_SP3_ENABLE[19]           - (RW) 0: Disable and clear BMC service period for BSSID 3 with invaliding BMC timeout event
                                     1: Enable BMC service period function for BSSID 3. BMC_SP start/stop condition is shown in the following table.
    BEACON_SP2_RESET[20]         - (WO) Write:
                                     0: No meaning
                                     1: Reset/Clear corresponding service period
    BMC_SP2_RESET[21]            - (WO) Write:
                                     0: No meaning
                                     1: Reset/Clear corresponding service period
    BEACON_SP3_RESET[22]         - (WO) Write:
                                     0: No meaning
                                     1: Reset/Clear corresponding service period
    BMC_SP3_RESET[23]            - (WO) Write:
                                     0: No meaning
                                     1: Reset/Clear corresponding service period
    BEACON_SP2[24]               - (RU) Reflects the current service period state for BSSID 2
    BMC_SP2[25]                  - (RU) Reflects the current service period state for BSSID 2
    BEACON_SP3[26]               - (RU) Reflects the current service period state for BSSID 3
    BMC_SP3[27]                  - (RU) Reflects the current service period state for BSSID 3
    TBTT2_RFON_SP_ENABLE[28]     - (RW) 0: Disable and clear TBTT RF service period for BSSID 2 with invaliding Green AP mode.
                                     1: Enable the TBTT RF service period function for BSSID 2 with validing Green AP mode.
    TBTT3_RFON_SP_ENABLE[29]     - (RW) 0: Disable and clear TBTT RF service period for BSSID 3 with invaliding Green AP mode.
                                     1: Enable the TBTT RF service period function for BSSID 3 with validing Green AP mode.
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SPCR_TBTT3_RFON_SP_ENABLE_ADDR         BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_TBTT3_RFON_SP_ENABLE_MASK         0x20000000                // TBTT3_RFON_SP_ENABLE[29]
#define BN0_WF_LPON_TOP_SPCR_TBTT3_RFON_SP_ENABLE_SHFT         29
#define BN0_WF_LPON_TOP_SPCR_TBTT2_RFON_SP_ENABLE_ADDR         BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_TBTT2_RFON_SP_ENABLE_MASK         0x10000000                // TBTT2_RFON_SP_ENABLE[28]
#define BN0_WF_LPON_TOP_SPCR_TBTT2_RFON_SP_ENABLE_SHFT         28
#define BN0_WF_LPON_TOP_SPCR_BMC_SP3_ADDR                      BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BMC_SP3_MASK                      0x08000000                // BMC_SP3[27]
#define BN0_WF_LPON_TOP_SPCR_BMC_SP3_SHFT                      27
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP3_ADDR                   BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP3_MASK                   0x04000000                // BEACON_SP3[26]
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP3_SHFT                   26
#define BN0_WF_LPON_TOP_SPCR_BMC_SP2_ADDR                      BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BMC_SP2_MASK                      0x02000000                // BMC_SP2[25]
#define BN0_WF_LPON_TOP_SPCR_BMC_SP2_SHFT                      25
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP2_ADDR                   BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP2_MASK                   0x01000000                // BEACON_SP2[24]
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP2_SHFT                   24
#define BN0_WF_LPON_TOP_SPCR_BMC_SP3_RESET_ADDR                BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BMC_SP3_RESET_MASK                0x00800000                // BMC_SP3_RESET[23]
#define BN0_WF_LPON_TOP_SPCR_BMC_SP3_RESET_SHFT                23
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP3_RESET_ADDR             BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP3_RESET_MASK             0x00400000                // BEACON_SP3_RESET[22]
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP3_RESET_SHFT             22
#define BN0_WF_LPON_TOP_SPCR_BMC_SP2_RESET_ADDR                BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BMC_SP2_RESET_MASK                0x00200000                // BMC_SP2_RESET[21]
#define BN0_WF_LPON_TOP_SPCR_BMC_SP2_RESET_SHFT                21
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP2_RESET_ADDR             BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP2_RESET_MASK             0x00100000                // BEACON_SP2_RESET[20]
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP2_RESET_SHFT             20
#define BN0_WF_LPON_TOP_SPCR_BMC_SP3_ENABLE_ADDR               BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BMC_SP3_ENABLE_MASK               0x00080000                // BMC_SP3_ENABLE[19]
#define BN0_WF_LPON_TOP_SPCR_BMC_SP3_ENABLE_SHFT               19
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP3_ENABLE_ADDR            BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP3_ENABLE_MASK            0x00040000                // BEACON_SP3_ENABLE[18]
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP3_ENABLE_SHFT            18
#define BN0_WF_LPON_TOP_SPCR_BMC_SP2_ENABLE_ADDR               BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BMC_SP2_ENABLE_MASK               0x00020000                // BMC_SP2_ENABLE[17]
#define BN0_WF_LPON_TOP_SPCR_BMC_SP2_ENABLE_SHFT               17
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP2_ENABLE_ADDR            BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP2_ENABLE_MASK            0x00010000                // BEACON_SP2_ENABLE[16]
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP2_ENABLE_SHFT            16
#define BN0_WF_LPON_TOP_SPCR_TBTT1_RFON_SP_ENABLE_ADDR         BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_TBTT1_RFON_SP_ENABLE_MASK         0x00002000                // TBTT1_RFON_SP_ENABLE[13]
#define BN0_WF_LPON_TOP_SPCR_TBTT1_RFON_SP_ENABLE_SHFT         13
#define BN0_WF_LPON_TOP_SPCR_TBTT0_RFON_SP_ENABLE_ADDR         BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_TBTT0_RFON_SP_ENABLE_MASK         0x00001000                // TBTT0_RFON_SP_ENABLE[12]
#define BN0_WF_LPON_TOP_SPCR_TBTT0_RFON_SP_ENABLE_SHFT         12
#define BN0_WF_LPON_TOP_SPCR_BMC_SP1_ADDR                      BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BMC_SP1_MASK                      0x00000800                // BMC_SP1[11]
#define BN0_WF_LPON_TOP_SPCR_BMC_SP1_SHFT                      11
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP1_ADDR                   BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP1_MASK                   0x00000400                // BEACON_SP1[10]
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP1_SHFT                   10
#define BN0_WF_LPON_TOP_SPCR_BMC_SP0_ADDR                      BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BMC_SP0_MASK                      0x00000200                // BMC_SP0[9]
#define BN0_WF_LPON_TOP_SPCR_BMC_SP0_SHFT                      9
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP0_ADDR                   BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP0_MASK                   0x00000100                // BEACON_SP0[8]
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP0_SHFT                   8
#define BN0_WF_LPON_TOP_SPCR_BMC_SP1_RESET_ADDR                BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BMC_SP1_RESET_MASK                0x00000080                // BMC_SP1_RESET[7]
#define BN0_WF_LPON_TOP_SPCR_BMC_SP1_RESET_SHFT                7
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP1_RESET_ADDR             BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP1_RESET_MASK             0x00000040                // BEACON_SP1_RESET[6]
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP1_RESET_SHFT             6
#define BN0_WF_LPON_TOP_SPCR_BMC_SP0_RESET_ADDR                BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BMC_SP0_RESET_MASK                0x00000020                // BMC_SP0_RESET[5]
#define BN0_WF_LPON_TOP_SPCR_BMC_SP0_RESET_SHFT                5
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP0_RESET_ADDR             BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP0_RESET_MASK             0x00000010                // BEACON_SP0_RESET[4]
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP0_RESET_SHFT             4
#define BN0_WF_LPON_TOP_SPCR_BMC_SP1_ENABLE_ADDR               BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BMC_SP1_ENABLE_MASK               0x00000008                // BMC_SP1_ENABLE[3]
#define BN0_WF_LPON_TOP_SPCR_BMC_SP1_ENABLE_SHFT               3
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP1_ENABLE_ADDR            BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP1_ENABLE_MASK            0x00000004                // BEACON_SP1_ENABLE[2]
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP1_ENABLE_SHFT            2
#define BN0_WF_LPON_TOP_SPCR_BMC_SP0_ENABLE_ADDR               BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BMC_SP0_ENABLE_MASK               0x00000002                // BMC_SP0_ENABLE[1]
#define BN0_WF_LPON_TOP_SPCR_BMC_SP0_ENABLE_SHFT               1
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP0_ENABLE_ADDR            BN0_WF_LPON_TOP_SPCR_ADDR
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP0_ENABLE_MASK            0x00000001                // BEACON_SP0_ENABLE[0]
#define BN0_WF_LPON_TOP_SPCR_BEACON_SP0_ENABLE_SHFT            0

/* =====================================================================================

  ---SPCR1 (0x820EB000 + 0x1ac)---

    NDPA_SP_ENABLE[0]            - (RW) 0: Disable and clear NDPA service period
                                     1: Enable NDPA service period function
    NDPA_SP_RESET[1]             - (WO) Write:
                                     0: No meaning
                                     1: Reset/Clear corresponding service period
    NDPA_SP[2]                   - (RU) Reflects the current NDPA service period state
    RESERVED3[31..3]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_SPCR1_NDPA_SP_ADDR                     BN0_WF_LPON_TOP_SPCR1_ADDR
#define BN0_WF_LPON_TOP_SPCR1_NDPA_SP_MASK                     0x00000004                // NDPA_SP[2]
#define BN0_WF_LPON_TOP_SPCR1_NDPA_SP_SHFT                     2
#define BN0_WF_LPON_TOP_SPCR1_NDPA_SP_RESET_ADDR               BN0_WF_LPON_TOP_SPCR1_ADDR
#define BN0_WF_LPON_TOP_SPCR1_NDPA_SP_RESET_MASK               0x00000002                // NDPA_SP_RESET[1]
#define BN0_WF_LPON_TOP_SPCR1_NDPA_SP_RESET_SHFT               1
#define BN0_WF_LPON_TOP_SPCR1_NDPA_SP_ENABLE_ADDR              BN0_WF_LPON_TOP_SPCR1_ADDR
#define BN0_WF_LPON_TOP_SPCR1_NDPA_SP_ENABLE_MASK              0x00000001                // NDPA_SP_ENABLE[0]
#define BN0_WF_LPON_TOP_SPCR1_NDPA_SP_ENABLE_SHFT              0

/* =====================================================================================

  ---BCNTR (0x820EB000 + 0x1b0)---

    BMC_MIN_TIME_LIMIT[5..0]     - (RW) Min. time for BMC timeout
                                     Unit: TU
                                     If there is any CCA (or mdrdy, by TCLCR. MIN_TIME_CTRL setting), txpe will occur and the local timeout counter will be reset.
    BMC_MIN_TIME_LIMIT_VALID[6]  - (RW) Indicates validation of BMC_min_time_limit
                                     If both BMC_max_time_limit_valid and BMC_min_time_limit_valid are 0, timeout will occur immediately.
    BMC_MAX_TIME_LIMIT_VALID[7]  - (RW) Indicates validation of BMC_max_time_limit
                                     If both BMC_max_time_limit_valid and BMC_min_time_limit_valid are 0, timeout will occur immediately.
    BMC_MAX_TIME_LIMIT[15..8]    - (RW) Max. time for the BMC timeout counter last
                                     Unit: 4TU
    BCN_MIN_TIME_LIMIT[21..16]   - (RW) Min. time for beacon timeout
                                     Unit: TU
                                     If there is any CCA (or mdrdy, by TCLCR. MIN_TIME_CTRL setting), txpe will occur and the local timeout counter will be reset.
    BCN_MIN_TIME_LIMIT_VALID[22] - (RW) Indicates validation of min_time_limit
                                     If both bcn_max_time_limit_valid and bcn_min_time_limit_valid are 0, timeout will occur immediately.
    BCN_MAX_TIME_LIMIT_VALID[23] - (RW) Indicates validation of bcn_max_time_limit
                                     If both bcn_max_time_limit_valid and bcn_min_time_limit_valid are 0, timeout will occur immediately.
    BCN_MAX_TIME_LIMIT[31..24]   - (RW) Max. time for beacon timeout
                                     Unit: 4TU

 =====================================================================================*/
#define BN0_WF_LPON_TOP_BCNTR_BCN_MAX_TIME_LIMIT_ADDR          BN0_WF_LPON_TOP_BCNTR_ADDR
#define BN0_WF_LPON_TOP_BCNTR_BCN_MAX_TIME_LIMIT_MASK          0xFF000000                // BCN_MAX_TIME_LIMIT[31..24]
#define BN0_WF_LPON_TOP_BCNTR_BCN_MAX_TIME_LIMIT_SHFT          24
#define BN0_WF_LPON_TOP_BCNTR_BCN_MAX_TIME_LIMIT_VALID_ADDR    BN0_WF_LPON_TOP_BCNTR_ADDR
#define BN0_WF_LPON_TOP_BCNTR_BCN_MAX_TIME_LIMIT_VALID_MASK    0x00800000                // BCN_MAX_TIME_LIMIT_VALID[23]
#define BN0_WF_LPON_TOP_BCNTR_BCN_MAX_TIME_LIMIT_VALID_SHFT    23
#define BN0_WF_LPON_TOP_BCNTR_BCN_MIN_TIME_LIMIT_VALID_ADDR    BN0_WF_LPON_TOP_BCNTR_ADDR
#define BN0_WF_LPON_TOP_BCNTR_BCN_MIN_TIME_LIMIT_VALID_MASK    0x00400000                // BCN_MIN_TIME_LIMIT_VALID[22]
#define BN0_WF_LPON_TOP_BCNTR_BCN_MIN_TIME_LIMIT_VALID_SHFT    22
#define BN0_WF_LPON_TOP_BCNTR_BCN_MIN_TIME_LIMIT_ADDR          BN0_WF_LPON_TOP_BCNTR_ADDR
#define BN0_WF_LPON_TOP_BCNTR_BCN_MIN_TIME_LIMIT_MASK          0x003F0000                // BCN_MIN_TIME_LIMIT[21..16]
#define BN0_WF_LPON_TOP_BCNTR_BCN_MIN_TIME_LIMIT_SHFT          16
#define BN0_WF_LPON_TOP_BCNTR_BMC_MAX_TIME_LIMIT_ADDR          BN0_WF_LPON_TOP_BCNTR_ADDR
#define BN0_WF_LPON_TOP_BCNTR_BMC_MAX_TIME_LIMIT_MASK          0x0000FF00                // BMC_MAX_TIME_LIMIT[15..8]
#define BN0_WF_LPON_TOP_BCNTR_BMC_MAX_TIME_LIMIT_SHFT          8
#define BN0_WF_LPON_TOP_BCNTR_BMC_MAX_TIME_LIMIT_VALID_ADDR    BN0_WF_LPON_TOP_BCNTR_ADDR
#define BN0_WF_LPON_TOP_BCNTR_BMC_MAX_TIME_LIMIT_VALID_MASK    0x00000080                // BMC_MAX_TIME_LIMIT_VALID[7]
#define BN0_WF_LPON_TOP_BCNTR_BMC_MAX_TIME_LIMIT_VALID_SHFT    7
#define BN0_WF_LPON_TOP_BCNTR_BMC_MIN_TIME_LIMIT_VALID_ADDR    BN0_WF_LPON_TOP_BCNTR_ADDR
#define BN0_WF_LPON_TOP_BCNTR_BMC_MIN_TIME_LIMIT_VALID_MASK    0x00000040                // BMC_MIN_TIME_LIMIT_VALID[6]
#define BN0_WF_LPON_TOP_BCNTR_BMC_MIN_TIME_LIMIT_VALID_SHFT    6
#define BN0_WF_LPON_TOP_BCNTR_BMC_MIN_TIME_LIMIT_ADDR          BN0_WF_LPON_TOP_BCNTR_ADDR
#define BN0_WF_LPON_TOP_BCNTR_BMC_MIN_TIME_LIMIT_MASK          0x0000003F                // BMC_MIN_TIME_LIMIT[5..0]
#define BN0_WF_LPON_TOP_BCNTR_BMC_MIN_TIME_LIMIT_SHFT          0

/* =====================================================================================

  ---TCLCR (0x820EB000 + 0x1b4)---

    BCN_TIMEOUT_COUNT_LIMIT[5..0] - (RW) Controls when to generate WIS0R.Bcn_Timeout
                                     6'd1: Wake up and generate interrupt at 1st timeout
                                     6'd2: Wake up and generate interrupt at 2nd timeout
                                     ...
                                     6'd63: Wake up and generate interrupt at 63rd timeout
                                     6'd0: No wakeup and will not generate interrupt
    BCN0_TIMEOUT_EVT_PAUSE[6]    - (RW) Pauses BCN0 timeout counter
    BCN1_TIMEOUT_EVT_PAUSE[7]    - (RW) Pauses BCN1 timeout counter
    BMC_TIMEOUT_COUNT_LIMIT[11..8] - (RW) Controls when to generate WIS0R.BMC_Timeout
                                     4'd1: Wake up and generate those interrupts at 1st timeout
                                     4'd2: Wake up and generate those interrupts at 2nd timeout
                                     ...
                                     4'd15: Wake up and generate those interrupts at 15th timeout
                                     4'd0: No wakeup and will not generate interrupt
    BCN2_TIMEOUT_EVT_PAUSE[12]   - (RW) Pauses BCN2 timeout counter
    BCN3_TIMEOUT_EVT_PAUSE[13]   - (RW) Pauses BCN3 timeout counter
    TIM0_TIMEOUT_EVT_PAUSE[14]   - (RW) Pauses TIM0 timeout counter
    TIM1_TIMEOUT_EVT_PAUSE[15]   - (RW) Pauses TIM1 timeout counter
    TIM_TIMEOUT_COUNT_LIMIT[21..16] - (RW) Same as BCN_TIMEOUT_COUNT_LIMIT
    TIM2_TIMEOUT_EVT_PAUSE[22]   - (RW) Pauses TIM2 timeout counter
    TIM3_TIMEOUT_EVT_PAUSE[23]   - (RW) Pauses TIM3 timeout counter
    TIM_BMC_TIMEOUT_COUNT_LIMIT[27..24] - (RW) Same as BMC_TIMEOUT_COUNT_LIMIT
    RESERVED28[28]               - (RO) Reserved bits
    TIM_TO_EVT_CNT_RESET_CTRL[29] - (WO) Write 1 to reset the timeout event counter, including both TIM and TIM_BMC timeout event counter.
                                     Writing 0 is meaningless. Read will return 0.
    MIN_TIME_CTRL[30]            - (RW) Selects mdrdy or CCA to be used for min. timer extension
                                     0: mdrdy assertion will be used to reset min. timer.
                                     1: CCA assertion will be used to reset min. timer.
    BCN_TO_EVT_CNT_RESET_CTRL[31] - (WO) Write 1 to reset the timeout event counter, including both beacon and BMC timeout event counter.
                                     Writing 0 is meaningless. Read will return 0.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TCLCR_BCN_TO_EVT_CNT_RESET_CTRL_ADDR   BN0_WF_LPON_TOP_TCLCR_ADDR
#define BN0_WF_LPON_TOP_TCLCR_BCN_TO_EVT_CNT_RESET_CTRL_MASK   0x80000000                // BCN_TO_EVT_CNT_RESET_CTRL[31]
#define BN0_WF_LPON_TOP_TCLCR_BCN_TO_EVT_CNT_RESET_CTRL_SHFT   31
#define BN0_WF_LPON_TOP_TCLCR_MIN_TIME_CTRL_ADDR               BN0_WF_LPON_TOP_TCLCR_ADDR
#define BN0_WF_LPON_TOP_TCLCR_MIN_TIME_CTRL_MASK               0x40000000                // MIN_TIME_CTRL[30]
#define BN0_WF_LPON_TOP_TCLCR_MIN_TIME_CTRL_SHFT               30
#define BN0_WF_LPON_TOP_TCLCR_TIM_TO_EVT_CNT_RESET_CTRL_ADDR   BN0_WF_LPON_TOP_TCLCR_ADDR
#define BN0_WF_LPON_TOP_TCLCR_TIM_TO_EVT_CNT_RESET_CTRL_MASK   0x20000000                // TIM_TO_EVT_CNT_RESET_CTRL[29]
#define BN0_WF_LPON_TOP_TCLCR_TIM_TO_EVT_CNT_RESET_CTRL_SHFT   29
#define BN0_WF_LPON_TOP_TCLCR_TIM_BMC_TIMEOUT_COUNT_LIMIT_ADDR BN0_WF_LPON_TOP_TCLCR_ADDR
#define BN0_WF_LPON_TOP_TCLCR_TIM_BMC_TIMEOUT_COUNT_LIMIT_MASK 0x0F000000                // TIM_BMC_TIMEOUT_COUNT_LIMIT[27..24]
#define BN0_WF_LPON_TOP_TCLCR_TIM_BMC_TIMEOUT_COUNT_LIMIT_SHFT 24
#define BN0_WF_LPON_TOP_TCLCR_TIM3_TIMEOUT_EVT_PAUSE_ADDR      BN0_WF_LPON_TOP_TCLCR_ADDR
#define BN0_WF_LPON_TOP_TCLCR_TIM3_TIMEOUT_EVT_PAUSE_MASK      0x00800000                // TIM3_TIMEOUT_EVT_PAUSE[23]
#define BN0_WF_LPON_TOP_TCLCR_TIM3_TIMEOUT_EVT_PAUSE_SHFT      23
#define BN0_WF_LPON_TOP_TCLCR_TIM2_TIMEOUT_EVT_PAUSE_ADDR      BN0_WF_LPON_TOP_TCLCR_ADDR
#define BN0_WF_LPON_TOP_TCLCR_TIM2_TIMEOUT_EVT_PAUSE_MASK      0x00400000                // TIM2_TIMEOUT_EVT_PAUSE[22]
#define BN0_WF_LPON_TOP_TCLCR_TIM2_TIMEOUT_EVT_PAUSE_SHFT      22
#define BN0_WF_LPON_TOP_TCLCR_TIM_TIMEOUT_COUNT_LIMIT_ADDR     BN0_WF_LPON_TOP_TCLCR_ADDR
#define BN0_WF_LPON_TOP_TCLCR_TIM_TIMEOUT_COUNT_LIMIT_MASK     0x003F0000                // TIM_TIMEOUT_COUNT_LIMIT[21..16]
#define BN0_WF_LPON_TOP_TCLCR_TIM_TIMEOUT_COUNT_LIMIT_SHFT     16
#define BN0_WF_LPON_TOP_TCLCR_TIM1_TIMEOUT_EVT_PAUSE_ADDR      BN0_WF_LPON_TOP_TCLCR_ADDR
#define BN0_WF_LPON_TOP_TCLCR_TIM1_TIMEOUT_EVT_PAUSE_MASK      0x00008000                // TIM1_TIMEOUT_EVT_PAUSE[15]
#define BN0_WF_LPON_TOP_TCLCR_TIM1_TIMEOUT_EVT_PAUSE_SHFT      15
#define BN0_WF_LPON_TOP_TCLCR_TIM0_TIMEOUT_EVT_PAUSE_ADDR      BN0_WF_LPON_TOP_TCLCR_ADDR
#define BN0_WF_LPON_TOP_TCLCR_TIM0_TIMEOUT_EVT_PAUSE_MASK      0x00004000                // TIM0_TIMEOUT_EVT_PAUSE[14]
#define BN0_WF_LPON_TOP_TCLCR_TIM0_TIMEOUT_EVT_PAUSE_SHFT      14
#define BN0_WF_LPON_TOP_TCLCR_BCN3_TIMEOUT_EVT_PAUSE_ADDR      BN0_WF_LPON_TOP_TCLCR_ADDR
#define BN0_WF_LPON_TOP_TCLCR_BCN3_TIMEOUT_EVT_PAUSE_MASK      0x00002000                // BCN3_TIMEOUT_EVT_PAUSE[13]
#define BN0_WF_LPON_TOP_TCLCR_BCN3_TIMEOUT_EVT_PAUSE_SHFT      13
#define BN0_WF_LPON_TOP_TCLCR_BCN2_TIMEOUT_EVT_PAUSE_ADDR      BN0_WF_LPON_TOP_TCLCR_ADDR
#define BN0_WF_LPON_TOP_TCLCR_BCN2_TIMEOUT_EVT_PAUSE_MASK      0x00001000                // BCN2_TIMEOUT_EVT_PAUSE[12]
#define BN0_WF_LPON_TOP_TCLCR_BCN2_TIMEOUT_EVT_PAUSE_SHFT      12
#define BN0_WF_LPON_TOP_TCLCR_BMC_TIMEOUT_COUNT_LIMIT_ADDR     BN0_WF_LPON_TOP_TCLCR_ADDR
#define BN0_WF_LPON_TOP_TCLCR_BMC_TIMEOUT_COUNT_LIMIT_MASK     0x00000F00                // BMC_TIMEOUT_COUNT_LIMIT[11..8]
#define BN0_WF_LPON_TOP_TCLCR_BMC_TIMEOUT_COUNT_LIMIT_SHFT     8
#define BN0_WF_LPON_TOP_TCLCR_BCN1_TIMEOUT_EVT_PAUSE_ADDR      BN0_WF_LPON_TOP_TCLCR_ADDR
#define BN0_WF_LPON_TOP_TCLCR_BCN1_TIMEOUT_EVT_PAUSE_MASK      0x00000080                // BCN1_TIMEOUT_EVT_PAUSE[7]
#define BN0_WF_LPON_TOP_TCLCR_BCN1_TIMEOUT_EVT_PAUSE_SHFT      7
#define BN0_WF_LPON_TOP_TCLCR_BCN0_TIMEOUT_EVT_PAUSE_ADDR      BN0_WF_LPON_TOP_TCLCR_ADDR
#define BN0_WF_LPON_TOP_TCLCR_BCN0_TIMEOUT_EVT_PAUSE_MASK      0x00000040                // BCN0_TIMEOUT_EVT_PAUSE[6]
#define BN0_WF_LPON_TOP_TCLCR_BCN0_TIMEOUT_EVT_PAUSE_SHFT      6
#define BN0_WF_LPON_TOP_TCLCR_BCN_TIMEOUT_COUNT_LIMIT_ADDR     BN0_WF_LPON_TOP_TCLCR_ADDR
#define BN0_WF_LPON_TOP_TCLCR_BCN_TIMEOUT_COUNT_LIMIT_MASK     0x0000003F                // BCN_TIMEOUT_COUNT_LIMIT[5..0]
#define BN0_WF_LPON_TOP_TCLCR_BCN_TIMEOUT_COUNT_LIMIT_SHFT     0

/* =====================================================================================

  ---BACKWARD (0x820EB000 + 0x1b8)---

    LPBCN_BACKWARD[0]            - (RW) Control the mac to phy interface signals :  mac2phy_rx_lpbcn
                                     1'b1 : the signal will toggle regardless of whether the signal "LGRX_BCN_EN" is set.
                                     1'b0 : the signal will toggle if "LGRX_BCN_EN" is enabled , else will be always 0
    RESERVED[30..1]              - (RW) RESERVED register
    REMAIN_ALWAYS_ON[31]         - (RW) Enable always check feature in TXTT remain time calculation state machine
                                     1: enable(every 1us_tick will trigger this feature)
                                     0: disable(check function will only be triggered by receiving beacon or probe response)

 =====================================================================================*/
#define BN0_WF_LPON_TOP_BACKWARD_REMAIN_ALWAYS_ON_ADDR         BN0_WF_LPON_TOP_BACKWARD_ADDR
#define BN0_WF_LPON_TOP_BACKWARD_REMAIN_ALWAYS_ON_MASK         0x80000000                // REMAIN_ALWAYS_ON[31]
#define BN0_WF_LPON_TOP_BACKWARD_REMAIN_ALWAYS_ON_SHFT         31
#define BN0_WF_LPON_TOP_BACKWARD_LPBCN_BACKWARD_ADDR           BN0_WF_LPON_TOP_BACKWARD_ADDR
#define BN0_WF_LPON_TOP_BACKWARD_LPBCN_BACKWARD_MASK           0x00000001                // LPBCN_BACKWARD[0]
#define BN0_WF_LPON_TOP_BACKWARD_LPBCN_BACKWARD_SHFT           0

/* =====================================================================================

  ---LGRX_BCNCR0 (0x820EB000 + 0x1bc)---

    LGRX_BCN_EN[0]               - (RW) Enables low power beacon RX function (low gain)
                                     0: Keep current gain setting
                                     1: Make current LNA operate at low gain mode to receive Beacon with lower power consumption
    LGRX_BCN_HWCTRL_EN[1]        - (RW) Indicated low power beacon RX function (low gain) is controlled by HW
                                     The function is enabled only when LGRX_BCN_EN is set to 1 already. 
                                     0: HW will not automatically control gain setting and keep low gain setting.
                                     1: HW will set to low gain as receiving Beacon, set to normal gain as BMC SP and set back to low gain after BMC SP is finished. In MT6630 case, after all 4 BSSID exit BMCSP, it will return to low gain RX setting. 
                                     If the number of lost beacon exceeds LGRX_BCN_LOST_CNT, HW will jump to normal gain state. HW will jump back to low gain state only both current RCPI exceeds LGRX_BCN_RCPI_THR and the number of received Beacon continuously exceeds LGRX_BCN_RCV_CNT.
    ALL_LGRX_LOW_GAIN_STS[2]     - (RU) low power beacon RX status
    RESERVED3[15..3]             - (RO) Reserved bits
    LGRX_BCN_LOST_CNT[23..16]    - (RW) Low power beacon RX function (low gain) lost Beacon count limit
    LGRX_BCN_RECEIVE_CNT[31..24] - (RW) Low power beacon RX function (low gain) received Beacon count limit

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_LGRX_BCN_RECEIVE_CNT_ADDR  BN0_WF_LPON_TOP_LGRX_BCNCR0_ADDR
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_LGRX_BCN_RECEIVE_CNT_MASK  0xFF000000                // LGRX_BCN_RECEIVE_CNT[31..24]
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_LGRX_BCN_RECEIVE_CNT_SHFT  24
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_LGRX_BCN_LOST_CNT_ADDR     BN0_WF_LPON_TOP_LGRX_BCNCR0_ADDR
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_LGRX_BCN_LOST_CNT_MASK     0x00FF0000                // LGRX_BCN_LOST_CNT[23..16]
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_LGRX_BCN_LOST_CNT_SHFT     16
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_ALL_LGRX_LOW_GAIN_STS_ADDR BN0_WF_LPON_TOP_LGRX_BCNCR0_ADDR
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_ALL_LGRX_LOW_GAIN_STS_MASK 0x00000004                // ALL_LGRX_LOW_GAIN_STS[2]
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_ALL_LGRX_LOW_GAIN_STS_SHFT 2
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_LGRX_BCN_HWCTRL_EN_ADDR    BN0_WF_LPON_TOP_LGRX_BCNCR0_ADDR
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_LGRX_BCN_HWCTRL_EN_MASK    0x00000002                // LGRX_BCN_HWCTRL_EN[1]
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_LGRX_BCN_HWCTRL_EN_SHFT    1
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_LGRX_BCN_EN_ADDR           BN0_WF_LPON_TOP_LGRX_BCNCR0_ADDR
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_LGRX_BCN_EN_MASK           0x00000001                // LGRX_BCN_EN[0]
#define BN0_WF_LPON_TOP_LGRX_BCNCR0_LGRX_BCN_EN_SHFT           0

/* =====================================================================================

  ---LGRX_BCNCR1 (0x820EB000 + 0x1c0)---

    LGRX_BCN_RCPI_THR0[9..0]     - (RW) Low power beacon RX function (low gain) RCPI0 threshold
    RESERVED10[15..10]           - (RO) Reserved bits
    LGRX_BCN_RCPI_THR1[25..16]   - (RW) Low power beacon RX function (low gain) RCPI1 threshold
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LGRX_BCNCR1_LGRX_BCN_RCPI_THR1_ADDR    BN0_WF_LPON_TOP_LGRX_BCNCR1_ADDR
#define BN0_WF_LPON_TOP_LGRX_BCNCR1_LGRX_BCN_RCPI_THR1_MASK    0x03FF0000                // LGRX_BCN_RCPI_THR1[25..16]
#define BN0_WF_LPON_TOP_LGRX_BCNCR1_LGRX_BCN_RCPI_THR1_SHFT    16
#define BN0_WF_LPON_TOP_LGRX_BCNCR1_LGRX_BCN_RCPI_THR0_ADDR    BN0_WF_LPON_TOP_LGRX_BCNCR1_ADDR
#define BN0_WF_LPON_TOP_LGRX_BCNCR1_LGRX_BCN_RCPI_THR0_MASK    0x000003FF                // LGRX_BCN_RCPI_THR0[9..0]
#define BN0_WF_LPON_TOP_LGRX_BCNCR1_LGRX_BCN_RCPI_THR0_SHFT    0

/* =====================================================================================

  ---LGRX_BCNCR2 (0x820EB000 + 0x1c4)---

    LGRX_BCN_RCPI_THR2[9..0]     - (RW) Low power beacon RX function (low gain) RCPI2 threshold
    RESERVED10[15..10]           - (RO) Reserved bits
    LGRX_BCN_RCPI_THR3[25..16]   - (RW) Low power beacon RX function (low gain) RCPI3 threshold
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LGRX_BCNCR2_LGRX_BCN_RCPI_THR3_ADDR    BN0_WF_LPON_TOP_LGRX_BCNCR2_ADDR
#define BN0_WF_LPON_TOP_LGRX_BCNCR2_LGRX_BCN_RCPI_THR3_MASK    0x03FF0000                // LGRX_BCN_RCPI_THR3[25..16]
#define BN0_WF_LPON_TOP_LGRX_BCNCR2_LGRX_BCN_RCPI_THR3_SHFT    16
#define BN0_WF_LPON_TOP_LGRX_BCNCR2_LGRX_BCN_RCPI_THR2_ADDR    BN0_WF_LPON_TOP_LGRX_BCNCR2_ADDR
#define BN0_WF_LPON_TOP_LGRX_BCNCR2_LGRX_BCN_RCPI_THR2_MASK    0x000003FF                // LGRX_BCN_RCPI_THR2[9..0]
#define BN0_WF_LPON_TOP_LGRX_BCNCR2_LGRX_BCN_RCPI_THR2_SHFT    0

/* =====================================================================================

  ---WLANCKCALCR0 (0x820EB000 + 0x1c8)---

    WLAN_CLK_CAL_OFST0[3..0]     - (RW) Indicates calibration timing offset value when LMAC_1X_MODE = 0
    WLAN_CLK_CAL_OFST1[7..4]     - (RW) Indicates calibration timing offset value when LMAC_1X_MODE = 1
    WLAN_CLK_CAL_OFST2[11..8]    - (RW) Indicates calibration timing offset value when LMAC_1X_MODE = 2
    WLAN_CLK_CAL_OFST3[15..12]   - (RW) Indicates calibration timing offset value when LMAC_1X_MODE = 3
    WLAN_CLK_CAL_OFST4[19..16]   - (RW) Indicates calibration timing offset value when LMAC_1X_MODE = 4
    RESERVED20[31..20]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_WLANCKCALCR0_WLAN_CLK_CAL_OFST4_ADDR   BN0_WF_LPON_TOP_WLANCKCALCR0_ADDR
#define BN0_WF_LPON_TOP_WLANCKCALCR0_WLAN_CLK_CAL_OFST4_MASK   0x000F0000                // WLAN_CLK_CAL_OFST4[19..16]
#define BN0_WF_LPON_TOP_WLANCKCALCR0_WLAN_CLK_CAL_OFST4_SHFT   16
#define BN0_WF_LPON_TOP_WLANCKCALCR0_WLAN_CLK_CAL_OFST3_ADDR   BN0_WF_LPON_TOP_WLANCKCALCR0_ADDR
#define BN0_WF_LPON_TOP_WLANCKCALCR0_WLAN_CLK_CAL_OFST3_MASK   0x0000F000                // WLAN_CLK_CAL_OFST3[15..12]
#define BN0_WF_LPON_TOP_WLANCKCALCR0_WLAN_CLK_CAL_OFST3_SHFT   12
#define BN0_WF_LPON_TOP_WLANCKCALCR0_WLAN_CLK_CAL_OFST2_ADDR   BN0_WF_LPON_TOP_WLANCKCALCR0_ADDR
#define BN0_WF_LPON_TOP_WLANCKCALCR0_WLAN_CLK_CAL_OFST2_MASK   0x00000F00                // WLAN_CLK_CAL_OFST2[11..8]
#define BN0_WF_LPON_TOP_WLANCKCALCR0_WLAN_CLK_CAL_OFST2_SHFT   8
#define BN0_WF_LPON_TOP_WLANCKCALCR0_WLAN_CLK_CAL_OFST1_ADDR   BN0_WF_LPON_TOP_WLANCKCALCR0_ADDR
#define BN0_WF_LPON_TOP_WLANCKCALCR0_WLAN_CLK_CAL_OFST1_MASK   0x000000F0                // WLAN_CLK_CAL_OFST1[7..4]
#define BN0_WF_LPON_TOP_WLANCKCALCR0_WLAN_CLK_CAL_OFST1_SHFT   4
#define BN0_WF_LPON_TOP_WLANCKCALCR0_WLAN_CLK_CAL_OFST0_ADDR   BN0_WF_LPON_TOP_WLANCKCALCR0_ADDR
#define BN0_WF_LPON_TOP_WLANCKCALCR0_WLAN_CLK_CAL_OFST0_MASK   0x0000000F                // WLAN_CLK_CAL_OFST0[3..0]
#define BN0_WF_LPON_TOP_WLANCKCALCR0_WLAN_CLK_CAL_OFST0_SHFT   0

/* =====================================================================================

  ---WLANCKCALCR1 (0x820EB000 + 0x1cc)---

    WLAN_CLK_DTIM_CAL_OFST0[4..0] - (RW) Indicates DTIM calibration timing offset value when LMAC_1X_MODE = 0
    WLAN_CLK_DTIM_CAL_OFST1[9..5] - (RW) Indicates DTIM calibration timing offset value when LMAC_1X_MODE = 1
    WLAN_CLK_DTIM_CAL_OFST2[14..10] - (RW) Indicates DTIM calibration timing offset value when LMAC_1X_MODE = 2
    RESERVED15[15]               - (RO) Reserved bits
    WLAN_CLK_DTIM_CAL_OFST3[20..16] - (RW) Indicates DTIM calibration timing offset value when LMAC_1X_MODE = 3
    WLAN_CLK_DTIM_CAL_OFST4[25..21] - (RW) Indicates DTIM calibration timing offset value when LMAC_1X_MODE = 4
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_WLANCKCALCR1_WLAN_CLK_DTIM_CAL_OFST4_ADDR BN0_WF_LPON_TOP_WLANCKCALCR1_ADDR
#define BN0_WF_LPON_TOP_WLANCKCALCR1_WLAN_CLK_DTIM_CAL_OFST4_MASK 0x03E00000                // WLAN_CLK_DTIM_CAL_OFST4[25..21]
#define BN0_WF_LPON_TOP_WLANCKCALCR1_WLAN_CLK_DTIM_CAL_OFST4_SHFT 21
#define BN0_WF_LPON_TOP_WLANCKCALCR1_WLAN_CLK_DTIM_CAL_OFST3_ADDR BN0_WF_LPON_TOP_WLANCKCALCR1_ADDR
#define BN0_WF_LPON_TOP_WLANCKCALCR1_WLAN_CLK_DTIM_CAL_OFST3_MASK 0x001F0000                // WLAN_CLK_DTIM_CAL_OFST3[20..16]
#define BN0_WF_LPON_TOP_WLANCKCALCR1_WLAN_CLK_DTIM_CAL_OFST3_SHFT 16
#define BN0_WF_LPON_TOP_WLANCKCALCR1_WLAN_CLK_DTIM_CAL_OFST2_ADDR BN0_WF_LPON_TOP_WLANCKCALCR1_ADDR
#define BN0_WF_LPON_TOP_WLANCKCALCR1_WLAN_CLK_DTIM_CAL_OFST2_MASK 0x00007C00                // WLAN_CLK_DTIM_CAL_OFST2[14..10]
#define BN0_WF_LPON_TOP_WLANCKCALCR1_WLAN_CLK_DTIM_CAL_OFST2_SHFT 10
#define BN0_WF_LPON_TOP_WLANCKCALCR1_WLAN_CLK_DTIM_CAL_OFST1_ADDR BN0_WF_LPON_TOP_WLANCKCALCR1_ADDR
#define BN0_WF_LPON_TOP_WLANCKCALCR1_WLAN_CLK_DTIM_CAL_OFST1_MASK 0x000003E0                // WLAN_CLK_DTIM_CAL_OFST1[9..5]
#define BN0_WF_LPON_TOP_WLANCKCALCR1_WLAN_CLK_DTIM_CAL_OFST1_SHFT 5
#define BN0_WF_LPON_TOP_WLANCKCALCR1_WLAN_CLK_DTIM_CAL_OFST0_ADDR BN0_WF_LPON_TOP_WLANCKCALCR1_ADDR
#define BN0_WF_LPON_TOP_WLANCKCALCR1_WLAN_CLK_DTIM_CAL_OFST0_MASK 0x0000001F                // WLAN_CLK_DTIM_CAL_OFST0[4..0]
#define BN0_WF_LPON_TOP_WLANCKCALCR1_WLAN_CLK_DTIM_CAL_OFST0_SHFT 0

/* =====================================================================================

  ---TIMSPCR (0x820EB000 + 0x1d0)---

    TIM_SP0_ENABLE[0]            - (RW) 0: Disable and clear beacon service period for BSSID 1 with invaliding beacon timeout event
    TIM_BMC_SP0_ENABLE[1]        - (RW) 1: Enable the beacon service period function for BSSID 1. TIM_SP start/stop condition is shown in the following table.
    TIM_SP1_ENABLE[2]            - (RW) 0: Disable and clear BMC service period for BSSID 1 with invaliding  BMC timeout event
    TIM_BMC_SP1_ENABLE[3]        - (RW) 1: Enable BMC service period function for BSSID 1. TIM_BMC_SP start/stop condition is shown in the following table.
    TIM_SP0_RESET[4]             - (WO) Write:
                                     0: No meaning
                                     1: Reset/Clear corresponding service period.
    TIM_BMC_SP0_RESET[5]         - (WO) Write:
                                     0: No meaning
                                     1: Reset/Clear corresponding service period
    TIM_SP1_RESET[6]             - (WO) Write:
                                     0: No meaning
                                     1: Reset/Clear corresponding service period.
    TIM_BMC_SP1_RESET[7]         - (WO) Write:
                                     0: No meaning
                                     1: Reset/Clear corresponding service period.
    TIM_SP0[8]                   - (RU) Reflects the current service period state for BSSID 0
    TIM_BMC_SP0[9]               - (RU) Reflects the current service period state for BSSID 0
    TIM_SP1[10]                  - (RU) Reflects the current service period state for BSSID 1
    TIM_BMC_SP1[11]              - (RU) Reflects the current service period state for BSSID 1
    TTTT0_RFON_SP_ENABLE[12]     - (RW) 0: Disable and clear TTTT RF service period for BSSID 0 with invaliding Green AP mode.
                                     1: Enable the TTTT RF service period function for BSSID 0 with validing Green AP mode.
    TTTT1_RFON_SP_ENABLE[13]     - (RW) 0: Disable and clear TTTT RF service period for BSSID 1 with invaliding Green AP mode.
                                     1: Enable the TTTT RF service period function for BSSID 1 with validing Green AP mode.
    RESERVED14[15..14]           - (RO) Reserved bits
    TIM_SP2_ENABLE[16]           - (RW) Same as TIM_SP0_ENABLE
    TIM_BMC_SP2_ENABLE[17]       - (RW) Same as TIM_BMC_SP0_ENABLE
    TIM_SP3_ENABLE[18]           - (RW) Same as TIM_SP1_ENABLE
    TIM_BMC_SP3_ENABLE[19]       - (RW) Same as TIM_BMC_SP1_ENABLE
    TIM_SP2_RESET[20]            - (WO) Same as TIM_SP0_RESET
    TIM_BMC_SP2_RESET[21]        - (WO) Same as TIM_BMC_SP0_RESET
    TIM_SP3_RESET[22]            - (WO) Same as TIM_SP1_RESET
    TIM_BMC_SP3_RESET[23]        - (WO) Same as TIM_BMC_SP1_RESET
    TIM_SP2[24]                  - (RU) Same as TIM_SP0
    TIM_BMC_SP2[25]              - (RU) Same as TIM_BMC_SP0
    TIM_SP3[26]                  - (RU) Same as TIM_SP1
    TIM_BMC_SP3[27]              - (RU) Same as TIM_BMC_SP1
    TTTT2_RFON_SP_ENABLE[28]     - (RW) 0: Disable and clear TTTT RF service period for BSSID 2 with invaliding Green AP mode.
                                     1: Enable the TTTT RF service period function for BSSID 2 with validing Green AP mode.
    TTTT3_RFON_SP_ENABLE[29]     - (RW) 0: Disable and clear TTTT RF service period for BSSID 3 with invaliding Green AP mode.
                                     1: Enable the TTTT RF service period function for BSSID 3 with validing Green AP mode.
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TIMSPCR_TTTT3_RFON_SP_ENABLE_ADDR      BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TTTT3_RFON_SP_ENABLE_MASK      0x20000000                // TTTT3_RFON_SP_ENABLE[29]
#define BN0_WF_LPON_TOP_TIMSPCR_TTTT3_RFON_SP_ENABLE_SHFT      29
#define BN0_WF_LPON_TOP_TIMSPCR_TTTT2_RFON_SP_ENABLE_ADDR      BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TTTT2_RFON_SP_ENABLE_MASK      0x10000000                // TTTT2_RFON_SP_ENABLE[28]
#define BN0_WF_LPON_TOP_TIMSPCR_TTTT2_RFON_SP_ENABLE_SHFT      28
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP3_ADDR               BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP3_MASK               0x08000000                // TIM_BMC_SP3[27]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP3_SHFT               27
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP3_ADDR                   BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP3_MASK                   0x04000000                // TIM_SP3[26]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP3_SHFT                   26
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP2_ADDR               BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP2_MASK               0x02000000                // TIM_BMC_SP2[25]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP2_SHFT               25
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP2_ADDR                   BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP2_MASK                   0x01000000                // TIM_SP2[24]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP2_SHFT                   24
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP3_RESET_ADDR         BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP3_RESET_MASK         0x00800000                // TIM_BMC_SP3_RESET[23]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP3_RESET_SHFT         23
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP3_RESET_ADDR             BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP3_RESET_MASK             0x00400000                // TIM_SP3_RESET[22]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP3_RESET_SHFT             22
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP2_RESET_ADDR         BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP2_RESET_MASK         0x00200000                // TIM_BMC_SP2_RESET[21]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP2_RESET_SHFT         21
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP2_RESET_ADDR             BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP2_RESET_MASK             0x00100000                // TIM_SP2_RESET[20]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP2_RESET_SHFT             20
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP3_ENABLE_ADDR        BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP3_ENABLE_MASK        0x00080000                // TIM_BMC_SP3_ENABLE[19]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP3_ENABLE_SHFT        19
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP3_ENABLE_ADDR            BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP3_ENABLE_MASK            0x00040000                // TIM_SP3_ENABLE[18]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP3_ENABLE_SHFT            18
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP2_ENABLE_ADDR        BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP2_ENABLE_MASK        0x00020000                // TIM_BMC_SP2_ENABLE[17]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP2_ENABLE_SHFT        17
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP2_ENABLE_ADDR            BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP2_ENABLE_MASK            0x00010000                // TIM_SP2_ENABLE[16]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP2_ENABLE_SHFT            16
#define BN0_WF_LPON_TOP_TIMSPCR_TTTT1_RFON_SP_ENABLE_ADDR      BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TTTT1_RFON_SP_ENABLE_MASK      0x00002000                // TTTT1_RFON_SP_ENABLE[13]
#define BN0_WF_LPON_TOP_TIMSPCR_TTTT1_RFON_SP_ENABLE_SHFT      13
#define BN0_WF_LPON_TOP_TIMSPCR_TTTT0_RFON_SP_ENABLE_ADDR      BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TTTT0_RFON_SP_ENABLE_MASK      0x00001000                // TTTT0_RFON_SP_ENABLE[12]
#define BN0_WF_LPON_TOP_TIMSPCR_TTTT0_RFON_SP_ENABLE_SHFT      12
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP1_ADDR               BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP1_MASK               0x00000800                // TIM_BMC_SP1[11]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP1_SHFT               11
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP1_ADDR                   BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP1_MASK                   0x00000400                // TIM_SP1[10]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP1_SHFT                   10
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP0_ADDR               BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP0_MASK               0x00000200                // TIM_BMC_SP0[9]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP0_SHFT               9
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP0_ADDR                   BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP0_MASK                   0x00000100                // TIM_SP0[8]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP0_SHFT                   8
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP1_RESET_ADDR         BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP1_RESET_MASK         0x00000080                // TIM_BMC_SP1_RESET[7]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP1_RESET_SHFT         7
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP1_RESET_ADDR             BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP1_RESET_MASK             0x00000040                // TIM_SP1_RESET[6]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP1_RESET_SHFT             6
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP0_RESET_ADDR         BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP0_RESET_MASK         0x00000020                // TIM_BMC_SP0_RESET[5]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP0_RESET_SHFT         5
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP0_RESET_ADDR             BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP0_RESET_MASK             0x00000010                // TIM_SP0_RESET[4]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP0_RESET_SHFT             4
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP1_ENABLE_ADDR        BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP1_ENABLE_MASK        0x00000008                // TIM_BMC_SP1_ENABLE[3]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP1_ENABLE_SHFT        3
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP1_ENABLE_ADDR            BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP1_ENABLE_MASK            0x00000004                // TIM_SP1_ENABLE[2]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP1_ENABLE_SHFT            2
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP0_ENABLE_ADDR        BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP0_ENABLE_MASK        0x00000002                // TIM_BMC_SP0_ENABLE[1]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_BMC_SP0_ENABLE_SHFT        1
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP0_ENABLE_ADDR            BN0_WF_LPON_TOP_TIMSPCR_ADDR
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP0_ENABLE_MASK            0x00000001                // TIM_SP0_ENABLE[0]
#define BN0_WF_LPON_TOP_TIMSPCR_TIM_SP0_ENABLE_SHFT            0

/* =====================================================================================

  ---CTBCNCR (0x820EB000 + 0x1d4)---

    CTBCN0_WAKEUP_NEXTDTIM[0]    - (RW) 0: Even when receiving critical beacon, it remains the original wakeup mechanism and time for BSSID 0.
                                     1: When receiving critical beacon, it will wake up at the next DTIM for BSSID 0.
    CTBCN1_WAKEUP_NEXTDTIM[1]    - (RW) 0: Even when receiving critical beacon, it remains the original wakeup mechanism and time for BSSID 1.
                                     1: When receiving critical beacon, it will wake up at the next DTIM for BSSID 1.
    CTBCN2_WAKEUP_NEXTDTIM[2]    - (RW) 0: Even when receiving critical beacon, it remains the original wakeup mechanism and time for BSSID 2.
                                     1: When receiving critical beacon, it will wake up at the next DTIM for BSSID 2.
    CTBCN3_WAKEUP_NEXTDTIM[3]    - (RW) 0: Even when receiving critical beacon, it remains the original wakeup. 
                                     1: When receiving critical beacon, it will wake up at the next DTIM for BSSID 3 mechanism and time for BSSID 3.
    RX_CRITICAL_BCN0_FLAG[4]     - (RU) During critical beacon RX, the flag becomes 1 to prepare wakeup for RX's next beacon as either the next DTIM or next wakeup event.
    RX_CRITICAL_BCN1_FLAG[5]     - (RU) Same as RX_CRITICAL_BCN0_FLAG
    RX_CRITICAL_BCN2_FLAG[6]     - (RU) Same as RX_CRITICAL_BCN0_FLAG
    RX_CRITICAL_BCN3_FLAG[7]     - (RU) Same as RX_CRITICAL_BCN0_FLAG
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_CTBCNCR_RX_CRITICAL_BCN3_FLAG_ADDR     BN0_WF_LPON_TOP_CTBCNCR_ADDR
#define BN0_WF_LPON_TOP_CTBCNCR_RX_CRITICAL_BCN3_FLAG_MASK     0x00000080                // RX_CRITICAL_BCN3_FLAG[7]
#define BN0_WF_LPON_TOP_CTBCNCR_RX_CRITICAL_BCN3_FLAG_SHFT     7
#define BN0_WF_LPON_TOP_CTBCNCR_RX_CRITICAL_BCN2_FLAG_ADDR     BN0_WF_LPON_TOP_CTBCNCR_ADDR
#define BN0_WF_LPON_TOP_CTBCNCR_RX_CRITICAL_BCN2_FLAG_MASK     0x00000040                // RX_CRITICAL_BCN2_FLAG[6]
#define BN0_WF_LPON_TOP_CTBCNCR_RX_CRITICAL_BCN2_FLAG_SHFT     6
#define BN0_WF_LPON_TOP_CTBCNCR_RX_CRITICAL_BCN1_FLAG_ADDR     BN0_WF_LPON_TOP_CTBCNCR_ADDR
#define BN0_WF_LPON_TOP_CTBCNCR_RX_CRITICAL_BCN1_FLAG_MASK     0x00000020                // RX_CRITICAL_BCN1_FLAG[5]
#define BN0_WF_LPON_TOP_CTBCNCR_RX_CRITICAL_BCN1_FLAG_SHFT     5
#define BN0_WF_LPON_TOP_CTBCNCR_RX_CRITICAL_BCN0_FLAG_ADDR     BN0_WF_LPON_TOP_CTBCNCR_ADDR
#define BN0_WF_LPON_TOP_CTBCNCR_RX_CRITICAL_BCN0_FLAG_MASK     0x00000010                // RX_CRITICAL_BCN0_FLAG[4]
#define BN0_WF_LPON_TOP_CTBCNCR_RX_CRITICAL_BCN0_FLAG_SHFT     4
#define BN0_WF_LPON_TOP_CTBCNCR_CTBCN3_WAKEUP_NEXTDTIM_ADDR    BN0_WF_LPON_TOP_CTBCNCR_ADDR
#define BN0_WF_LPON_TOP_CTBCNCR_CTBCN3_WAKEUP_NEXTDTIM_MASK    0x00000008                // CTBCN3_WAKEUP_NEXTDTIM[3]
#define BN0_WF_LPON_TOP_CTBCNCR_CTBCN3_WAKEUP_NEXTDTIM_SHFT    3
#define BN0_WF_LPON_TOP_CTBCNCR_CTBCN2_WAKEUP_NEXTDTIM_ADDR    BN0_WF_LPON_TOP_CTBCNCR_ADDR
#define BN0_WF_LPON_TOP_CTBCNCR_CTBCN2_WAKEUP_NEXTDTIM_MASK    0x00000004                // CTBCN2_WAKEUP_NEXTDTIM[2]
#define BN0_WF_LPON_TOP_CTBCNCR_CTBCN2_WAKEUP_NEXTDTIM_SHFT    2
#define BN0_WF_LPON_TOP_CTBCNCR_CTBCN1_WAKEUP_NEXTDTIM_ADDR    BN0_WF_LPON_TOP_CTBCNCR_ADDR
#define BN0_WF_LPON_TOP_CTBCNCR_CTBCN1_WAKEUP_NEXTDTIM_MASK    0x00000002                // CTBCN1_WAKEUP_NEXTDTIM[1]
#define BN0_WF_LPON_TOP_CTBCNCR_CTBCN1_WAKEUP_NEXTDTIM_SHFT    1
#define BN0_WF_LPON_TOP_CTBCNCR_CTBCN0_WAKEUP_NEXTDTIM_ADDR    BN0_WF_LPON_TOP_CTBCNCR_ADDR
#define BN0_WF_LPON_TOP_CTBCNCR_CTBCN0_WAKEUP_NEXTDTIM_MASK    0x00000001                // CTBCN0_WAKEUP_NEXTDTIM[0]
#define BN0_WF_LPON_TOP_CTBCNCR_CTBCN0_WAKEUP_NEXTDTIM_SHFT    0

/* =====================================================================================

  ---LBCNTOR (0x820EB000 + 0x1d8)---

    BCN0_TOUT_EVT_CNT[5..0]      - (RW) HW current Beacon 0 timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED6[7..6]              - (RO) Reserved bits
    BCN1_TOUT_EVT_CNT[13..8]     - (RW) HW current Beacon 1 timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED14[15..14]           - (RO) Reserved bits
    BCN2_TOUT_EVT_CNT[21..16]    - (RW) HW current Beacon 2 timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED22[23..22]           - (RO) Reserved bits
    BCN3_TOUT_EVT_CNT[29..24]    - (RW) HW current Beacon 3 timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LBCNTOR_BCN3_TOUT_EVT_CNT_ADDR         BN0_WF_LPON_TOP_LBCNTOR_ADDR
#define BN0_WF_LPON_TOP_LBCNTOR_BCN3_TOUT_EVT_CNT_MASK         0x3F000000                // BCN3_TOUT_EVT_CNT[29..24]
#define BN0_WF_LPON_TOP_LBCNTOR_BCN3_TOUT_EVT_CNT_SHFT         24
#define BN0_WF_LPON_TOP_LBCNTOR_BCN2_TOUT_EVT_CNT_ADDR         BN0_WF_LPON_TOP_LBCNTOR_ADDR
#define BN0_WF_LPON_TOP_LBCNTOR_BCN2_TOUT_EVT_CNT_MASK         0x003F0000                // BCN2_TOUT_EVT_CNT[21..16]
#define BN0_WF_LPON_TOP_LBCNTOR_BCN2_TOUT_EVT_CNT_SHFT         16
#define BN0_WF_LPON_TOP_LBCNTOR_BCN1_TOUT_EVT_CNT_ADDR         BN0_WF_LPON_TOP_LBCNTOR_ADDR
#define BN0_WF_LPON_TOP_LBCNTOR_BCN1_TOUT_EVT_CNT_MASK         0x00003F00                // BCN1_TOUT_EVT_CNT[13..8]
#define BN0_WF_LPON_TOP_LBCNTOR_BCN1_TOUT_EVT_CNT_SHFT         8
#define BN0_WF_LPON_TOP_LBCNTOR_BCN0_TOUT_EVT_CNT_ADDR         BN0_WF_LPON_TOP_LBCNTOR_ADDR
#define BN0_WF_LPON_TOP_LBCNTOR_BCN0_TOUT_EVT_CNT_MASK         0x0000003F                // BCN0_TOUT_EVT_CNT[5..0]
#define BN0_WF_LPON_TOP_LBCNTOR_BCN0_TOUT_EVT_CNT_SHFT         0

/* =====================================================================================

  ---LTIMTOR (0x820EB000 + 0x1dc)---

    TIM0_TOUT_EVT_CNT[5..0]      - (RW) HW current TIM 0 timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED6[7..6]              - (RO) Reserved bits
    TIM1_TOUT_EVT_CNT[13..8]     - (RW) HW current TIM 1 timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED14[15..14]           - (RO) Reserved bits
    TIM2_TOUT_EVT_CNT[21..16]    - (RW) HW current TIM 2 timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED22[23..22]           - (RO) Reserved bits
    TIM3_TOUT_EVT_CNT[29..24]    - (RW) HW current TIM 3 timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LTIMTOR_TIM3_TOUT_EVT_CNT_ADDR         BN0_WF_LPON_TOP_LTIMTOR_ADDR
#define BN0_WF_LPON_TOP_LTIMTOR_TIM3_TOUT_EVT_CNT_MASK         0x3F000000                // TIM3_TOUT_EVT_CNT[29..24]
#define BN0_WF_LPON_TOP_LTIMTOR_TIM3_TOUT_EVT_CNT_SHFT         24
#define BN0_WF_LPON_TOP_LTIMTOR_TIM2_TOUT_EVT_CNT_ADDR         BN0_WF_LPON_TOP_LTIMTOR_ADDR
#define BN0_WF_LPON_TOP_LTIMTOR_TIM2_TOUT_EVT_CNT_MASK         0x003F0000                // TIM2_TOUT_EVT_CNT[21..16]
#define BN0_WF_LPON_TOP_LTIMTOR_TIM2_TOUT_EVT_CNT_SHFT         16
#define BN0_WF_LPON_TOP_LTIMTOR_TIM1_TOUT_EVT_CNT_ADDR         BN0_WF_LPON_TOP_LTIMTOR_ADDR
#define BN0_WF_LPON_TOP_LTIMTOR_TIM1_TOUT_EVT_CNT_MASK         0x00003F00                // TIM1_TOUT_EVT_CNT[13..8]
#define BN0_WF_LPON_TOP_LTIMTOR_TIM1_TOUT_EVT_CNT_SHFT         8
#define BN0_WF_LPON_TOP_LTIMTOR_TIM0_TOUT_EVT_CNT_ADDR         BN0_WF_LPON_TOP_LTIMTOR_ADDR
#define BN0_WF_LPON_TOP_LTIMTOR_TIM0_TOUT_EVT_CNT_MASK         0x0000003F                // TIM0_TOUT_EVT_CNT[5..0]
#define BN0_WF_LPON_TOP_LTIMTOR_TIM0_TOUT_EVT_CNT_SHFT         0

/* =====================================================================================

  ---LBMCTOR (0x820EB000 + 0x1e0)---

    BMC0_TOUT_EVT_CNT[3..0]      - (RW) HW current BMC 0 timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED4[7..4]              - (RO) Reserved bits
    BMC1_TOUT_EVT_CNT[11..8]     - (RW) HW current BMC 1 timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED12[15..12]           - (RO) Reserved bits
    BMC2_TOUT_EVT_CNT[19..16]    - (RW) HW current BMC 2 timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED20[23..20]           - (RO) Reserved bits
    BMC3_TOUT_EVT_CNT[27..24]    - (RW) HW current BMC 3 timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LBMCTOR_BMC3_TOUT_EVT_CNT_ADDR         BN0_WF_LPON_TOP_LBMCTOR_ADDR
#define BN0_WF_LPON_TOP_LBMCTOR_BMC3_TOUT_EVT_CNT_MASK         0x0F000000                // BMC3_TOUT_EVT_CNT[27..24]
#define BN0_WF_LPON_TOP_LBMCTOR_BMC3_TOUT_EVT_CNT_SHFT         24
#define BN0_WF_LPON_TOP_LBMCTOR_BMC2_TOUT_EVT_CNT_ADDR         BN0_WF_LPON_TOP_LBMCTOR_ADDR
#define BN0_WF_LPON_TOP_LBMCTOR_BMC2_TOUT_EVT_CNT_MASK         0x000F0000                // BMC2_TOUT_EVT_CNT[19..16]
#define BN0_WF_LPON_TOP_LBMCTOR_BMC2_TOUT_EVT_CNT_SHFT         16
#define BN0_WF_LPON_TOP_LBMCTOR_BMC1_TOUT_EVT_CNT_ADDR         BN0_WF_LPON_TOP_LBMCTOR_ADDR
#define BN0_WF_LPON_TOP_LBMCTOR_BMC1_TOUT_EVT_CNT_MASK         0x00000F00                // BMC1_TOUT_EVT_CNT[11..8]
#define BN0_WF_LPON_TOP_LBMCTOR_BMC1_TOUT_EVT_CNT_SHFT         8
#define BN0_WF_LPON_TOP_LBMCTOR_BMC0_TOUT_EVT_CNT_ADDR         BN0_WF_LPON_TOP_LBMCTOR_ADDR
#define BN0_WF_LPON_TOP_LBMCTOR_BMC0_TOUT_EVT_CNT_MASK         0x0000000F                // BMC0_TOUT_EVT_CNT[3..0]
#define BN0_WF_LPON_TOP_LBMCTOR_BMC0_TOUT_EVT_CNT_SHFT         0

/* =====================================================================================

  ---LTMBCTOR (0x820EB000 + 0x1e4)---

    TBMC0_TOUT_EVT_CNT[3..0]     - (RW) HW current TIM BMC 0 TIM timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED4[7..4]              - (RO) Reserved bits
    TBMC1_TOUT_EVT_CNT[11..8]    - (RW) HW current TIM BMC 1 TIM timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED12[15..12]           - (RO) Reserved bits
    TBMC2_TOUT_EVT_CNT[19..16]   - (RW) HW current TIM BMC 2 TIM timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED20[23..20]           - (RO) Reserved bits
    TBMC3_TOUT_EVT_CNT[27..24]   - (RW) HW current TIM BMC 3 TIM timeout count
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LTMBCTOR_TBMC3_TOUT_EVT_CNT_ADDR       BN0_WF_LPON_TOP_LTMBCTOR_ADDR
#define BN0_WF_LPON_TOP_LTMBCTOR_TBMC3_TOUT_EVT_CNT_MASK       0x0F000000                // TBMC3_TOUT_EVT_CNT[27..24]
#define BN0_WF_LPON_TOP_LTMBCTOR_TBMC3_TOUT_EVT_CNT_SHFT       24
#define BN0_WF_LPON_TOP_LTMBCTOR_TBMC2_TOUT_EVT_CNT_ADDR       BN0_WF_LPON_TOP_LTMBCTOR_ADDR
#define BN0_WF_LPON_TOP_LTMBCTOR_TBMC2_TOUT_EVT_CNT_MASK       0x000F0000                // TBMC2_TOUT_EVT_CNT[19..16]
#define BN0_WF_LPON_TOP_LTMBCTOR_TBMC2_TOUT_EVT_CNT_SHFT       16
#define BN0_WF_LPON_TOP_LTMBCTOR_TBMC1_TOUT_EVT_CNT_ADDR       BN0_WF_LPON_TOP_LTMBCTOR_ADDR
#define BN0_WF_LPON_TOP_LTMBCTOR_TBMC1_TOUT_EVT_CNT_MASK       0x00000F00                // TBMC1_TOUT_EVT_CNT[11..8]
#define BN0_WF_LPON_TOP_LTMBCTOR_TBMC1_TOUT_EVT_CNT_SHFT       8
#define BN0_WF_LPON_TOP_LTMBCTOR_TBMC0_TOUT_EVT_CNT_ADDR       BN0_WF_LPON_TOP_LTMBCTOR_ADDR
#define BN0_WF_LPON_TOP_LTMBCTOR_TBMC0_TOUT_EVT_CNT_MASK       0x0000000F                // TBMC0_TOUT_EVT_CNT[3..0]
#define BN0_WF_LPON_TOP_LTMBCTOR_TBMC0_TOUT_EVT_CNT_SHFT       0

/* =====================================================================================

  ---LLGRBRR (0x820EB000 + 0x1e8)---

    LGBCN0_RCV_CNT[7..0]         - (RW) HW current received BCN 0 count for Low Power RX function
                                     Mainly used for CMDBT backup/restore usage.
    LGBCN1_RCV_CNT[15..8]        - (RW) HW current received BCN 1 count for Low Power RX function
                                     Mainly used for CMDBT backup/restore usage.
    LGBCN2_RCV_CNT[23..16]       - (RW) HW current received BCN 2 count for Low Power RX function
                                     Mainly used for CMDBT backup/restore usage.
    LGBCN3_RCV_CNT[31..24]       - (RW) HW current received BCN 3 count for Low Power RX function
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LLGRBRR_LGBCN3_RCV_CNT_ADDR            BN0_WF_LPON_TOP_LLGRBRR_ADDR
#define BN0_WF_LPON_TOP_LLGRBRR_LGBCN3_RCV_CNT_MASK            0xFF000000                // LGBCN3_RCV_CNT[31..24]
#define BN0_WF_LPON_TOP_LLGRBRR_LGBCN3_RCV_CNT_SHFT            24
#define BN0_WF_LPON_TOP_LLGRBRR_LGBCN2_RCV_CNT_ADDR            BN0_WF_LPON_TOP_LLGRBRR_ADDR
#define BN0_WF_LPON_TOP_LLGRBRR_LGBCN2_RCV_CNT_MASK            0x00FF0000                // LGBCN2_RCV_CNT[23..16]
#define BN0_WF_LPON_TOP_LLGRBRR_LGBCN2_RCV_CNT_SHFT            16
#define BN0_WF_LPON_TOP_LLGRBRR_LGBCN1_RCV_CNT_ADDR            BN0_WF_LPON_TOP_LLGRBRR_ADDR
#define BN0_WF_LPON_TOP_LLGRBRR_LGBCN1_RCV_CNT_MASK            0x0000FF00                // LGBCN1_RCV_CNT[15..8]
#define BN0_WF_LPON_TOP_LLGRBRR_LGBCN1_RCV_CNT_SHFT            8
#define BN0_WF_LPON_TOP_LLGRBRR_LGBCN0_RCV_CNT_ADDR            BN0_WF_LPON_TOP_LLGRBRR_ADDR
#define BN0_WF_LPON_TOP_LLGRBRR_LGBCN0_RCV_CNT_MASK            0x000000FF                // LGBCN0_RCV_CNT[7..0]
#define BN0_WF_LPON_TOP_LLGRBRR_LGBCN0_RCV_CNT_SHFT            0

/* =====================================================================================

  ---LLGRBLR (0x820EB000 + 0x1ec)---

    LGBCN0_LOST_CNT[7..0]        - (RW) HW current lost BCN 0 count for Low Power RX function
                                     Mainly used for CMDBT backup/restore usage.
    LGBCN1_LOST_CNT[15..8]       - (RW) HW current lost BCN 1 count for Low Power RX function
                                     Mainly used for CMDBT backup/restore usage.
    LGBCN2_LOST_CNT[23..16]      - (RW) HW current lost BCN 2 count for Low Power RX function
                                     Mainly used for CMDBT backup/restore usage.
    LGBCN3_LOST_CNT[31..24]      - (RW) HW current lost BCN 3 count for Low Power RX function
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LLGRBLR_LGBCN3_LOST_CNT_ADDR           BN0_WF_LPON_TOP_LLGRBLR_ADDR
#define BN0_WF_LPON_TOP_LLGRBLR_LGBCN3_LOST_CNT_MASK           0xFF000000                // LGBCN3_LOST_CNT[31..24]
#define BN0_WF_LPON_TOP_LLGRBLR_LGBCN3_LOST_CNT_SHFT           24
#define BN0_WF_LPON_TOP_LLGRBLR_LGBCN2_LOST_CNT_ADDR           BN0_WF_LPON_TOP_LLGRBLR_ADDR
#define BN0_WF_LPON_TOP_LLGRBLR_LGBCN2_LOST_CNT_MASK           0x00FF0000                // LGBCN2_LOST_CNT[23..16]
#define BN0_WF_LPON_TOP_LLGRBLR_LGBCN2_LOST_CNT_SHFT           16
#define BN0_WF_LPON_TOP_LLGRBLR_LGBCN1_LOST_CNT_ADDR           BN0_WF_LPON_TOP_LLGRBLR_ADDR
#define BN0_WF_LPON_TOP_LLGRBLR_LGBCN1_LOST_CNT_MASK           0x0000FF00                // LGBCN1_LOST_CNT[15..8]
#define BN0_WF_LPON_TOP_LLGRBLR_LGBCN1_LOST_CNT_SHFT           8
#define BN0_WF_LPON_TOP_LLGRBLR_LGBCN0_LOST_CNT_ADDR           BN0_WF_LPON_TOP_LLGRBLR_ADDR
#define BN0_WF_LPON_TOP_LLGRBLR_LGBCN0_LOST_CNT_MASK           0x000000FF                // LGBCN0_LOST_CNT[7..0]
#define BN0_WF_LPON_TOP_LLGRBLR_LGBCN0_LOST_CNT_SHFT           0

/* =====================================================================================

  ---LDTIMCR (0x820EB000 + 0x1f0)---

    HW_DTIM_CNT0[7..0]           - (RW) HW local DTIM0 counter value
                                     Mainly used for CMDBT backup/restore usage.
    HW_DTIM_CNT1[15..8]          - (RW) HW local DTIM1 counter value
                                     Mainly used for CMDBT backup/restore usage.
    HW_DTIM_CNT2[23..16]         - (RW) HW local DTIM2 counter value
                                     Mainly used for CMDBT backup/restore usage.
    HW_DTIM_CNT3[31..24]         - (RW) HW local DTIM3 counter value
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LDTIMCR_HW_DTIM_CNT3_ADDR              BN0_WF_LPON_TOP_LDTIMCR_ADDR
#define BN0_WF_LPON_TOP_LDTIMCR_HW_DTIM_CNT3_MASK              0xFF000000                // HW_DTIM_CNT3[31..24]
#define BN0_WF_LPON_TOP_LDTIMCR_HW_DTIM_CNT3_SHFT              24
#define BN0_WF_LPON_TOP_LDTIMCR_HW_DTIM_CNT2_ADDR              BN0_WF_LPON_TOP_LDTIMCR_ADDR
#define BN0_WF_LPON_TOP_LDTIMCR_HW_DTIM_CNT2_MASK              0x00FF0000                // HW_DTIM_CNT2[23..16]
#define BN0_WF_LPON_TOP_LDTIMCR_HW_DTIM_CNT2_SHFT              16
#define BN0_WF_LPON_TOP_LDTIMCR_HW_DTIM_CNT1_ADDR              BN0_WF_LPON_TOP_LDTIMCR_ADDR
#define BN0_WF_LPON_TOP_LDTIMCR_HW_DTIM_CNT1_MASK              0x0000FF00                // HW_DTIM_CNT1[15..8]
#define BN0_WF_LPON_TOP_LDTIMCR_HW_DTIM_CNT1_SHFT              8
#define BN0_WF_LPON_TOP_LDTIMCR_HW_DTIM_CNT0_ADDR              BN0_WF_LPON_TOP_LDTIMCR_ADDR
#define BN0_WF_LPON_TOP_LDTIMCR_HW_DTIM_CNT0_MASK              0x000000FF                // HW_DTIM_CNT0[7..0]
#define BN0_WF_LPON_TOP_LDTIMCR_HW_DTIM_CNT0_SHFT              0

/* =====================================================================================

  ---LMTBDTCR (0x820EB000 + 0x1f4)---

    HW_DTIMWAKEUP_CNT0[2..0]     - (RW) HW local mDTIM0 counter value
                                     Mainly used for CMDBT backup/restore usage.
    HW_TBTTWAKEUP_CNT0[6..3]     - (RW) HW local mTBTT0 counter value
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED7[7]                 - (RO) Reserved bits
    HW_DTIMWAKEUP_CNT1[10..8]    - (RW) HW local mDTIM1 counter value
                                     Mainly used for CMDBT backup/restore usage.
    HW_TBTTWAKEUP_CNT1[14..11]   - (RW) HW local mTBTT1 counter value
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED15[15]               - (RO) Reserved bits
    HW_DTIMWAKEUP_CNT2[18..16]   - (RW) HW local mDTIM2 counter value
                                     Mainly used for CMDBT backup/restore usage.
    HW_TBTTWAKEUP_CNT2[22..19]   - (RW) HW local mTBTT2 counter value
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED23[23]               - (RO) Reserved bits
    HW_DTIMWAKEUP_CNT3[26..24]   - (RW) HW local mDTIM3 counter value
                                     Mainly used for CMDBT backup/restore usage.
    HW_TBTTWAKEUP_CNT3[30..27]   - (RW) HW local mTBTT3 counter value
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_TBTTWAKEUP_CNT3_ADDR       BN0_WF_LPON_TOP_LMTBDTCR_ADDR
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_TBTTWAKEUP_CNT3_MASK       0x78000000                // HW_TBTTWAKEUP_CNT3[30..27]
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_TBTTWAKEUP_CNT3_SHFT       27
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_DTIMWAKEUP_CNT3_ADDR       BN0_WF_LPON_TOP_LMTBDTCR_ADDR
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_DTIMWAKEUP_CNT3_MASK       0x07000000                // HW_DTIMWAKEUP_CNT3[26..24]
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_DTIMWAKEUP_CNT3_SHFT       24
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_TBTTWAKEUP_CNT2_ADDR       BN0_WF_LPON_TOP_LMTBDTCR_ADDR
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_TBTTWAKEUP_CNT2_MASK       0x00780000                // HW_TBTTWAKEUP_CNT2[22..19]
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_TBTTWAKEUP_CNT2_SHFT       19
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_DTIMWAKEUP_CNT2_ADDR       BN0_WF_LPON_TOP_LMTBDTCR_ADDR
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_DTIMWAKEUP_CNT2_MASK       0x00070000                // HW_DTIMWAKEUP_CNT2[18..16]
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_DTIMWAKEUP_CNT2_SHFT       16
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_TBTTWAKEUP_CNT1_ADDR       BN0_WF_LPON_TOP_LMTBDTCR_ADDR
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_TBTTWAKEUP_CNT1_MASK       0x00007800                // HW_TBTTWAKEUP_CNT1[14..11]
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_TBTTWAKEUP_CNT1_SHFT       11
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_DTIMWAKEUP_CNT1_ADDR       BN0_WF_LPON_TOP_LMTBDTCR_ADDR
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_DTIMWAKEUP_CNT1_MASK       0x00000700                // HW_DTIMWAKEUP_CNT1[10..8]
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_DTIMWAKEUP_CNT1_SHFT       8
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_TBTTWAKEUP_CNT0_ADDR       BN0_WF_LPON_TOP_LMTBDTCR_ADDR
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_TBTTWAKEUP_CNT0_MASK       0x00000078                // HW_TBTTWAKEUP_CNT0[6..3]
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_TBTTWAKEUP_CNT0_SHFT       3
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_DTIMWAKEUP_CNT0_ADDR       BN0_WF_LPON_TOP_LMTBDTCR_ADDR
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_DTIMWAKEUP_CNT0_MASK       0x00000007                // HW_DTIMWAKEUP_CNT0[2..0]
#define BN0_WF_LPON_TOP_LMTBDTCR_HW_DTIMWAKEUP_CNT0_SHFT       0

/* =====================================================================================

  ---BUSY_SEL (0x820EB000 + 0x1f8)---

    WTBL_TOP_BUSY[0]             - (RO) WTBL_TOP_BUSY
    ETXBF_BFER_BUSY[1]           - (RO) ETXBF_BFER_BUSY
    ETXBF_BFEE_BUSY[2]           - (RO) ETXBF_BFEE_BUSY
    RMAC_BUSY[3]                 - (RO) RMAC_BUSY
    TMAC_BUSY[4]                 - (RO) TMAC_BUSY
    TRB_BUSY[5]                  - (RO) TRB_BUSY
    DMA_BUSY[6]                  - (RO) DMA_BUSY
    AGG_BUSY[7]                  - (RO) AGG_BUSY
    UMAC_TX_AGG_BUSY[8]          - (RO) UMAC_TX_AGG_BUSY
    IND_ALL_TIMER_BUSY[9]        - (RO) IND_ALL_TIMER_BUSY
    RESERVED10[30..10]           - (RO) Reserved bits
    LP_CR_AGG_BUSY_LEGACY[31]    - (RW) LP_CR_AGG_BUSY_LEGACY

 =====================================================================================*/
#define BN0_WF_LPON_TOP_BUSY_SEL_LP_CR_AGG_BUSY_LEGACY_ADDR    BN0_WF_LPON_TOP_BUSY_SEL_ADDR
#define BN0_WF_LPON_TOP_BUSY_SEL_LP_CR_AGG_BUSY_LEGACY_MASK    0x80000000                // LP_CR_AGG_BUSY_LEGACY[31]
#define BN0_WF_LPON_TOP_BUSY_SEL_LP_CR_AGG_BUSY_LEGACY_SHFT    31
#define BN0_WF_LPON_TOP_BUSY_SEL_IND_ALL_TIMER_BUSY_ADDR       BN0_WF_LPON_TOP_BUSY_SEL_ADDR
#define BN0_WF_LPON_TOP_BUSY_SEL_IND_ALL_TIMER_BUSY_MASK       0x00000200                // IND_ALL_TIMER_BUSY[9]
#define BN0_WF_LPON_TOP_BUSY_SEL_IND_ALL_TIMER_BUSY_SHFT       9
#define BN0_WF_LPON_TOP_BUSY_SEL_UMAC_TX_AGG_BUSY_ADDR         BN0_WF_LPON_TOP_BUSY_SEL_ADDR
#define BN0_WF_LPON_TOP_BUSY_SEL_UMAC_TX_AGG_BUSY_MASK         0x00000100                // UMAC_TX_AGG_BUSY[8]
#define BN0_WF_LPON_TOP_BUSY_SEL_UMAC_TX_AGG_BUSY_SHFT         8
#define BN0_WF_LPON_TOP_BUSY_SEL_AGG_BUSY_ADDR                 BN0_WF_LPON_TOP_BUSY_SEL_ADDR
#define BN0_WF_LPON_TOP_BUSY_SEL_AGG_BUSY_MASK                 0x00000080                // AGG_BUSY[7]
#define BN0_WF_LPON_TOP_BUSY_SEL_AGG_BUSY_SHFT                 7
#define BN0_WF_LPON_TOP_BUSY_SEL_DMA_BUSY_ADDR                 BN0_WF_LPON_TOP_BUSY_SEL_ADDR
#define BN0_WF_LPON_TOP_BUSY_SEL_DMA_BUSY_MASK                 0x00000040                // DMA_BUSY[6]
#define BN0_WF_LPON_TOP_BUSY_SEL_DMA_BUSY_SHFT                 6
#define BN0_WF_LPON_TOP_BUSY_SEL_TRB_BUSY_ADDR                 BN0_WF_LPON_TOP_BUSY_SEL_ADDR
#define BN0_WF_LPON_TOP_BUSY_SEL_TRB_BUSY_MASK                 0x00000020                // TRB_BUSY[5]
#define BN0_WF_LPON_TOP_BUSY_SEL_TRB_BUSY_SHFT                 5
#define BN0_WF_LPON_TOP_BUSY_SEL_TMAC_BUSY_ADDR                BN0_WF_LPON_TOP_BUSY_SEL_ADDR
#define BN0_WF_LPON_TOP_BUSY_SEL_TMAC_BUSY_MASK                0x00000010                // TMAC_BUSY[4]
#define BN0_WF_LPON_TOP_BUSY_SEL_TMAC_BUSY_SHFT                4
#define BN0_WF_LPON_TOP_BUSY_SEL_RMAC_BUSY_ADDR                BN0_WF_LPON_TOP_BUSY_SEL_ADDR
#define BN0_WF_LPON_TOP_BUSY_SEL_RMAC_BUSY_MASK                0x00000008                // RMAC_BUSY[3]
#define BN0_WF_LPON_TOP_BUSY_SEL_RMAC_BUSY_SHFT                3
#define BN0_WF_LPON_TOP_BUSY_SEL_ETXBF_BFEE_BUSY_ADDR          BN0_WF_LPON_TOP_BUSY_SEL_ADDR
#define BN0_WF_LPON_TOP_BUSY_SEL_ETXBF_BFEE_BUSY_MASK          0x00000004                // ETXBF_BFEE_BUSY[2]
#define BN0_WF_LPON_TOP_BUSY_SEL_ETXBF_BFEE_BUSY_SHFT          2
#define BN0_WF_LPON_TOP_BUSY_SEL_ETXBF_BFER_BUSY_ADDR          BN0_WF_LPON_TOP_BUSY_SEL_ADDR
#define BN0_WF_LPON_TOP_BUSY_SEL_ETXBF_BFER_BUSY_MASK          0x00000002                // ETXBF_BFER_BUSY[1]
#define BN0_WF_LPON_TOP_BUSY_SEL_ETXBF_BFER_BUSY_SHFT          1
#define BN0_WF_LPON_TOP_BUSY_SEL_WTBL_TOP_BUSY_ADDR            BN0_WF_LPON_TOP_BUSY_SEL_ADDR
#define BN0_WF_LPON_TOP_BUSY_SEL_WTBL_TOP_BUSY_MASK            0x00000001                // WTBL_TOP_BUSY[0]
#define BN0_WF_LPON_TOP_BUSY_SEL_WTBL_TOP_BUSY_SHFT            0

/* =====================================================================================

  ---LFBCR0 (0x820EB000 + 0x1fc)---

    FB_WAKE_CNT0[4..0]           - (RW) This field indicates the local wakeup counter 0 value to receive full beacon
                                     0. As the value equal to PB_WAKE_PERIOD_RXFB: 
                                     (1) The counter will be remained and wait until a full beacon or reset by SW.
                                     (2) LP will inform RMAC to receive a full beacon in any case. 
                                     (3) The next wakeup time for receiving a full beacon could be configured by CR FB_WAKEUP_MODE
                                     1. As receiving Partial beacon: the counter adds 1
                                     2. As receiving Partial beacon but TIM matched (CRC OK): RMAC will receive the full beacon and reset the counter
                                     3. As receiving Partial beacon but TIM matched (CRC Fail):
                                     RMAC will receive the full beacon and the counter adds 1
                                     4. Not receiving any beacon and SP Timeout occurs:
                                     the counter adds 1
                                     (It is mainly used for CMDBT backup and restore usage)
    LP_FULL_BCN0_EN[5]           - (RW) This field indicates the real full beacon counter window of BSSID0. As the value is 1, it means LP will wake up to receive a full Beacon by the definition of FB_WAKEUP_MODE. However, the value of 0 means LP use full will wake up as normal.
                                     (It is mainly used for CMDBT backup and restore usage)
    RESERVED6[7..6]              - (RO) Reserved bits
    FB_WAKE_CNT1[12..8]          - (RW) This field indicates the local wakeup counter 1 value to receive full beacon, same as FB_WAKE_CNT0
                                     (It is mainly used for CMDBT backup and restore usage)
    LP_FULL_BCN1_EN[13]          - (RW) This field indicates the real full beacon counter window of BSSID1. As the value is 1, it means LP will wake up to receive a full Beacon by the definition of FB_WAKEUP_MODE. However, the value of 0 means LP use full will wake up as normal.
                                     (It is mainly used for CMDBT backup and restore usage)
    RESERVED14[15..14]           - (RO) Reserved bits
    FB_WAKE_CNT2[20..16]         - (RW) This field indicates the local wakeup counter 2 value to receive full beacon, same as FB_WAKE_CNT0
                                     (It is mainly used for CMDBT backup and restore usage)
    LP_FULL_BCN2_EN[21]          - (RW) This field indicates the real full beacon counter window of BSSID2. As the value is 1, it means LP will wake up to receive a full Beacon by the definition of FB_WAKEUP_MODE. However, the value of 0 means LP use full will wake up as normal.
                                     (It is mainly used for CMDBT backup and restore usage)
    RESERVED22[23..22]           - (RO) Reserved bits
    FB_WAKE_CNT3[28..24]         - (RW) This field indicates the local wakeup counter 3 value to receive full beacon, same as FB_WAKE_CNT0
                                     (It is mainly used for CMDBT backup and restore usage)
    LP_FULL_BCN3_EN[29]          - (RW) This field indicates the real full beacon counter window of BSSID3. As the value is 1, it means LP will wake up to receive a full Beacon by the definition of FB_WAKEUP_MODE. However, the value of 0 means LP use full will wake up as normal.
                                     (It is mainly used for CMDBT backup and restore usage)
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_LFBCR0_LP_FULL_BCN3_EN_ADDR            BN0_WF_LPON_TOP_LFBCR0_ADDR
#define BN0_WF_LPON_TOP_LFBCR0_LP_FULL_BCN3_EN_MASK            0x20000000                // LP_FULL_BCN3_EN[29]
#define BN0_WF_LPON_TOP_LFBCR0_LP_FULL_BCN3_EN_SHFT            29
#define BN0_WF_LPON_TOP_LFBCR0_FB_WAKE_CNT3_ADDR               BN0_WF_LPON_TOP_LFBCR0_ADDR
#define BN0_WF_LPON_TOP_LFBCR0_FB_WAKE_CNT3_MASK               0x1F000000                // FB_WAKE_CNT3[28..24]
#define BN0_WF_LPON_TOP_LFBCR0_FB_WAKE_CNT3_SHFT               24
#define BN0_WF_LPON_TOP_LFBCR0_LP_FULL_BCN2_EN_ADDR            BN0_WF_LPON_TOP_LFBCR0_ADDR
#define BN0_WF_LPON_TOP_LFBCR0_LP_FULL_BCN2_EN_MASK            0x00200000                // LP_FULL_BCN2_EN[21]
#define BN0_WF_LPON_TOP_LFBCR0_LP_FULL_BCN2_EN_SHFT            21
#define BN0_WF_LPON_TOP_LFBCR0_FB_WAKE_CNT2_ADDR               BN0_WF_LPON_TOP_LFBCR0_ADDR
#define BN0_WF_LPON_TOP_LFBCR0_FB_WAKE_CNT2_MASK               0x001F0000                // FB_WAKE_CNT2[20..16]
#define BN0_WF_LPON_TOP_LFBCR0_FB_WAKE_CNT2_SHFT               16
#define BN0_WF_LPON_TOP_LFBCR0_LP_FULL_BCN1_EN_ADDR            BN0_WF_LPON_TOP_LFBCR0_ADDR
#define BN0_WF_LPON_TOP_LFBCR0_LP_FULL_BCN1_EN_MASK            0x00002000                // LP_FULL_BCN1_EN[13]
#define BN0_WF_LPON_TOP_LFBCR0_LP_FULL_BCN1_EN_SHFT            13
#define BN0_WF_LPON_TOP_LFBCR0_FB_WAKE_CNT1_ADDR               BN0_WF_LPON_TOP_LFBCR0_ADDR
#define BN0_WF_LPON_TOP_LFBCR0_FB_WAKE_CNT1_MASK               0x00001F00                // FB_WAKE_CNT1[12..8]
#define BN0_WF_LPON_TOP_LFBCR0_FB_WAKE_CNT1_SHFT               8
#define BN0_WF_LPON_TOP_LFBCR0_LP_FULL_BCN0_EN_ADDR            BN0_WF_LPON_TOP_LFBCR0_ADDR
#define BN0_WF_LPON_TOP_LFBCR0_LP_FULL_BCN0_EN_MASK            0x00000020                // LP_FULL_BCN0_EN[5]
#define BN0_WF_LPON_TOP_LFBCR0_LP_FULL_BCN0_EN_SHFT            5
#define BN0_WF_LPON_TOP_LFBCR0_FB_WAKE_CNT0_ADDR               BN0_WF_LPON_TOP_LFBCR0_ADDR
#define BN0_WF_LPON_TOP_LFBCR0_FB_WAKE_CNT0_MASK               0x0000001F                // FB_WAKE_CNT0[4..0]
#define BN0_WF_LPON_TOP_LFBCR0_FB_WAKE_CNT0_SHFT               0

/* =====================================================================================

  ---PBCR0 (0x820EB000 + 0x200)---

    PB_EN[3..0]                  - (RW) This field indicates the enable of corresponded BSSID partial beacon feature 
                                     0: disable this feature
                                     1: enable this feature 
                                     While this feature is enabled, LP and RMAC should ignore other hash content checking and only check BSSID and TIM IE of the beacon. If BSSID is matched and TIM IE did not indicate any UC or BMC packets, LP should drop this beacon and enter sleep state immediately
    PB_UPDATE_TSF[7..4]          - (RW) This field indicates the enable for updating TSF of corresponded BSSID partial beacon 
                                     0: not update
                                     1: update it
    PB_UPDATE_DTIM[11..8]        - (RW) This field indicates the enable for updating DTIM of corresponded BSSID partial beacon
                                     0: not update
                                     1: update it
    RESERVED12[14..12]           - (RO) Reserved bits
    FB_WAKEUP_MODE[15]           - (RW) This field indicates the next wakeup time as the value of FB_WAKE_CNT0~3 equal to PB_WAKE_PERIOD_RXFB
                                     0: Wakeup as next TBTT 
                                     1:Wakeup as next DTIM/mDTIM based on setting 
                                     (if only mDTIM enable and mTBTT/FMS are disable)
    PB_WAKE_PERIOD_RXFB[20..16]  - (RW) This field indicates the Wakeup period which will force to receive a full beacon (normally set value equal to 5)
                                     0: always not force to receive the full beacon
                                     1~31: force to receive a full beacon after continually receiving partial beacons for x times by corresponded BSSID
    LP_PARTIAL_BCN0_EN[21]       - (RO) This field indicates the real partial beacon window from LP to RMAC of BSSID0 as TBTT0 occurs. As the value is 1, it means RMAC use partial beacon method to receive Beacon. However, the value of 0 means RMAC use full beacon method to receive beacon as normal.
    LP_PARTIAL_BCN1_EN[22]       - (RO) This field indicates the real partial beacon window from LP to RMAC of BSSID1 as TBTT1 occurs. As the value is 1, it means RMAC use partial beacon method to receive Beacon. However, the value of 0 means RMAC use full beacon method to receive beacon as normal.
    LP_PARTIAL_BCN2_EN[23]       - (RO) This field indicates the real partial beacon window from LP to RMAC of BSSID2 as TBTT2 occurs. As the value is 1, it means RMAC use partial beacon method to receive Beacon. However, the value of 0 means RMAC use full beacon method to receive beacon as normal.
    LP_PARTIAL_BCN3_EN[24]       - (RO) This field indicates the real partial beacon window from LP to RMAC of BSSID3 as TBTT3 occurs. As the value is 1, it means RMAC use partial beacon method to receive Beacon. However, the value of 0 means RMAC use full beacon method to receive beacon as normal.
    WAKE_CNT0_RST[25]            - (WO) This field indicates the reset for LP_PARTIAL_BCN0_EN
                                     1: reset
                                     0:meaningless
    WAKE_CNT1_RST[26]            - (WO) This field indicates the reset for LP_PARTIAL_BCN1_EN
                                     1: reset
                                     0:meaningless
    WAKE_CNT2_RST[27]            - (WO) This field indicates the reset for LP_PARTIAL_BCN2_EN
                                     1: reset
                                     0:meaningless
    WAKE_CNT3_RST[28]            - (WO) This field indicates the reset for LP_PARTIAL_BCN3_EN
                                     1: reset
                                     0:meaningless
    BTIM_DTIM_UPATE_CHK[29]      - (RW) This field indicates enable LP check DTIM count accuracy from tim broadcast update. As enable is 1, unreasonable DTIM counter of Beacon will not update and may trigger WISR5 DTIM_CHK_INT. As enable is 0, as same as original behavior.
                                     0: disable
                                     1: enable
    BCN_DTIM_UPATE_CHK[30]       - (RW) This field indicates enable LP check DTIM count accuracy from  beacon update. As enable is 1, unreasonable DTIM counter of Beacon will not update and may trigger WISR5 DTIM_CHK_INT. As enable is 0, as same as original behavior.
                                     0: disable
                                     1: enable
    PB_DTIM_UPATE_CHK[31]        - (RW) This field indicates enable LP check DTIM count accuracy from partial beacon update. As enable is 1, unreasonable DTIM counter of Beacon will not update and may trigger WISR5 DTIM_CHK_INT. As enable is 0, as same as original behavior.
                                     0: disable
                                     1: enable

 =====================================================================================*/
#define BN0_WF_LPON_TOP_PBCR0_PB_DTIM_UPATE_CHK_ADDR           BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_PB_DTIM_UPATE_CHK_MASK           0x80000000                // PB_DTIM_UPATE_CHK[31]
#define BN0_WF_LPON_TOP_PBCR0_PB_DTIM_UPATE_CHK_SHFT           31
#define BN0_WF_LPON_TOP_PBCR0_BCN_DTIM_UPATE_CHK_ADDR          BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_BCN_DTIM_UPATE_CHK_MASK          0x40000000                // BCN_DTIM_UPATE_CHK[30]
#define BN0_WF_LPON_TOP_PBCR0_BCN_DTIM_UPATE_CHK_SHFT          30
#define BN0_WF_LPON_TOP_PBCR0_BTIM_DTIM_UPATE_CHK_ADDR         BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_BTIM_DTIM_UPATE_CHK_MASK         0x20000000                // BTIM_DTIM_UPATE_CHK[29]
#define BN0_WF_LPON_TOP_PBCR0_BTIM_DTIM_UPATE_CHK_SHFT         29
#define BN0_WF_LPON_TOP_PBCR0_WAKE_CNT3_RST_ADDR               BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_WAKE_CNT3_RST_MASK               0x10000000                // WAKE_CNT3_RST[28]
#define BN0_WF_LPON_TOP_PBCR0_WAKE_CNT3_RST_SHFT               28
#define BN0_WF_LPON_TOP_PBCR0_WAKE_CNT2_RST_ADDR               BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_WAKE_CNT2_RST_MASK               0x08000000                // WAKE_CNT2_RST[27]
#define BN0_WF_LPON_TOP_PBCR0_WAKE_CNT2_RST_SHFT               27
#define BN0_WF_LPON_TOP_PBCR0_WAKE_CNT1_RST_ADDR               BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_WAKE_CNT1_RST_MASK               0x04000000                // WAKE_CNT1_RST[26]
#define BN0_WF_LPON_TOP_PBCR0_WAKE_CNT1_RST_SHFT               26
#define BN0_WF_LPON_TOP_PBCR0_WAKE_CNT0_RST_ADDR               BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_WAKE_CNT0_RST_MASK               0x02000000                // WAKE_CNT0_RST[25]
#define BN0_WF_LPON_TOP_PBCR0_WAKE_CNT0_RST_SHFT               25
#define BN0_WF_LPON_TOP_PBCR0_LP_PARTIAL_BCN3_EN_ADDR          BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_LP_PARTIAL_BCN3_EN_MASK          0x01000000                // LP_PARTIAL_BCN3_EN[24]
#define BN0_WF_LPON_TOP_PBCR0_LP_PARTIAL_BCN3_EN_SHFT          24
#define BN0_WF_LPON_TOP_PBCR0_LP_PARTIAL_BCN2_EN_ADDR          BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_LP_PARTIAL_BCN2_EN_MASK          0x00800000                // LP_PARTIAL_BCN2_EN[23]
#define BN0_WF_LPON_TOP_PBCR0_LP_PARTIAL_BCN2_EN_SHFT          23
#define BN0_WF_LPON_TOP_PBCR0_LP_PARTIAL_BCN1_EN_ADDR          BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_LP_PARTIAL_BCN1_EN_MASK          0x00400000                // LP_PARTIAL_BCN1_EN[22]
#define BN0_WF_LPON_TOP_PBCR0_LP_PARTIAL_BCN1_EN_SHFT          22
#define BN0_WF_LPON_TOP_PBCR0_LP_PARTIAL_BCN0_EN_ADDR          BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_LP_PARTIAL_BCN0_EN_MASK          0x00200000                // LP_PARTIAL_BCN0_EN[21]
#define BN0_WF_LPON_TOP_PBCR0_LP_PARTIAL_BCN0_EN_SHFT          21
#define BN0_WF_LPON_TOP_PBCR0_PB_WAKE_PERIOD_RXFB_ADDR         BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_PB_WAKE_PERIOD_RXFB_MASK         0x001F0000                // PB_WAKE_PERIOD_RXFB[20..16]
#define BN0_WF_LPON_TOP_PBCR0_PB_WAKE_PERIOD_RXFB_SHFT         16
#define BN0_WF_LPON_TOP_PBCR0_FB_WAKEUP_MODE_ADDR              BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_FB_WAKEUP_MODE_MASK              0x00008000                // FB_WAKEUP_MODE[15]
#define BN0_WF_LPON_TOP_PBCR0_FB_WAKEUP_MODE_SHFT              15
#define BN0_WF_LPON_TOP_PBCR0_PB_UPDATE_DTIM_ADDR              BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_PB_UPDATE_DTIM_MASK              0x00000F00                // PB_UPDATE_DTIM[11..8]
#define BN0_WF_LPON_TOP_PBCR0_PB_UPDATE_DTIM_SHFT              8
#define BN0_WF_LPON_TOP_PBCR0_PB_UPDATE_TSF_ADDR               BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_PB_UPDATE_TSF_MASK               0x000000F0                // PB_UPDATE_TSF[7..4]
#define BN0_WF_LPON_TOP_PBCR0_PB_UPDATE_TSF_SHFT               4
#define BN0_WF_LPON_TOP_PBCR0_PB_EN_ADDR                       BN0_WF_LPON_TOP_PBCR0_ADDR
#define BN0_WF_LPON_TOP_PBCR0_PB_EN_MASK                       0x0000000F                // PB_EN[3..0]
#define BN0_WF_LPON_TOP_PBCR0_PB_EN_SHFT                       0

/* =====================================================================================

  ---NANCR0 (0x820EB000 + 0x204)---

    NAN_BAND_EN_SEL[1..0]        - (RW) This field indicates the band 
                                     The value:
                                     0: NAN disabled
                                     1: NAN is enabled in band 2P4G only. FW will get INT of TBTT timer in corresponded BSSID (by RMAC NAN_BSSID_SEL)
                                     2: NAN is enabled in band 5G only. FW will get INT of TTTT timer in corresponded BSSID (by RMAC NAN_BSSID_SEL)
                                     3: NAN are enabled in both bands 2P4G and 5G. FW will get INT of corresponded band. (2P4G by TBTT timer, 5G by TTTT timer) in corresponded BSSID (by RMAC NAN_BSSID_SEL)
    NAN_2P4G_DW[2]               - (RO) This field indicates the DW flag during 2.4G band 
                                     The NAN_BAND_EN_SEL must equal to 1 or 3
                                     As the value is 1, it mean within 2P4G DW
    NAN_5G_DW[3]                 - (RO) This field indicates the DW flag during 5G band 
                                     The NAN_BAND_EN_SEL must equal to 2 or 3
                                     As the value is 1, it mean within 5G DW
    T3_START_DBG[4]              - (RO) This field indicates the NAN t3 start
    NBCN_START_DBG[5]            - (RO) This field indicates the NAN nbcn start
    RESERVED6[7..6]              - (RO) Reserved bits
    NAN_DW_LEN[12..8]            - (RW) This field indicates the DW length in unit of TU, (normally set value equal to 16)
    RESERVED13[15..13]           - (RO) Reserved bits
    NAN_DW_CNT[25..16]           - (RO) This field indicates the NAN DW counter bit [9:0] (unit 32 us)
    RESERVED26[28..26]           - (RO) Reserved bits
    NAN_5G_DW_END_INT_EN[29]     - (RW) This field indicates the nan_5g_dw_end INT enable
    NAN_2P4G_DW_END_INT_EN[30]   - (RW) This field indicates the nan_2p4g_dw_end INT enable
    NAN_DW_RST[31]               - (WO) This field indicates the reset for NAN_DW_CNT
                                     1: reset
                                     0:meaningless

 =====================================================================================*/
#define BN0_WF_LPON_TOP_NANCR0_NAN_DW_RST_ADDR                 BN0_WF_LPON_TOP_NANCR0_ADDR
#define BN0_WF_LPON_TOP_NANCR0_NAN_DW_RST_MASK                 0x80000000                // NAN_DW_RST[31]
#define BN0_WF_LPON_TOP_NANCR0_NAN_DW_RST_SHFT                 31
#define BN0_WF_LPON_TOP_NANCR0_NAN_2P4G_DW_END_INT_EN_ADDR     BN0_WF_LPON_TOP_NANCR0_ADDR
#define BN0_WF_LPON_TOP_NANCR0_NAN_2P4G_DW_END_INT_EN_MASK     0x40000000                // NAN_2P4G_DW_END_INT_EN[30]
#define BN0_WF_LPON_TOP_NANCR0_NAN_2P4G_DW_END_INT_EN_SHFT     30
#define BN0_WF_LPON_TOP_NANCR0_NAN_5G_DW_END_INT_EN_ADDR       BN0_WF_LPON_TOP_NANCR0_ADDR
#define BN0_WF_LPON_TOP_NANCR0_NAN_5G_DW_END_INT_EN_MASK       0x20000000                // NAN_5G_DW_END_INT_EN[29]
#define BN0_WF_LPON_TOP_NANCR0_NAN_5G_DW_END_INT_EN_SHFT       29
#define BN0_WF_LPON_TOP_NANCR0_NAN_DW_CNT_ADDR                 BN0_WF_LPON_TOP_NANCR0_ADDR
#define BN0_WF_LPON_TOP_NANCR0_NAN_DW_CNT_MASK                 0x03FF0000                // NAN_DW_CNT[25..16]
#define BN0_WF_LPON_TOP_NANCR0_NAN_DW_CNT_SHFT                 16
#define BN0_WF_LPON_TOP_NANCR0_NAN_DW_LEN_ADDR                 BN0_WF_LPON_TOP_NANCR0_ADDR
#define BN0_WF_LPON_TOP_NANCR0_NAN_DW_LEN_MASK                 0x00001F00                // NAN_DW_LEN[12..8]
#define BN0_WF_LPON_TOP_NANCR0_NAN_DW_LEN_SHFT                 8
#define BN0_WF_LPON_TOP_NANCR0_NBCN_START_DBG_ADDR             BN0_WF_LPON_TOP_NANCR0_ADDR
#define BN0_WF_LPON_TOP_NANCR0_NBCN_START_DBG_MASK             0x00000020                // NBCN_START_DBG[5]
#define BN0_WF_LPON_TOP_NANCR0_NBCN_START_DBG_SHFT             5
#define BN0_WF_LPON_TOP_NANCR0_T3_START_DBG_ADDR               BN0_WF_LPON_TOP_NANCR0_ADDR
#define BN0_WF_LPON_TOP_NANCR0_T3_START_DBG_MASK               0x00000010                // T3_START_DBG[4]
#define BN0_WF_LPON_TOP_NANCR0_T3_START_DBG_SHFT               4
#define BN0_WF_LPON_TOP_NANCR0_NAN_5G_DW_ADDR                  BN0_WF_LPON_TOP_NANCR0_ADDR
#define BN0_WF_LPON_TOP_NANCR0_NAN_5G_DW_MASK                  0x00000008                // NAN_5G_DW[3]
#define BN0_WF_LPON_TOP_NANCR0_NAN_5G_DW_SHFT                  3
#define BN0_WF_LPON_TOP_NANCR0_NAN_2P4G_DW_ADDR                BN0_WF_LPON_TOP_NANCR0_ADDR
#define BN0_WF_LPON_TOP_NANCR0_NAN_2P4G_DW_MASK                0x00000004                // NAN_2P4G_DW[2]
#define BN0_WF_LPON_TOP_NANCR0_NAN_2P4G_DW_SHFT                2
#define BN0_WF_LPON_TOP_NANCR0_NAN_BAND_EN_SEL_ADDR            BN0_WF_LPON_TOP_NANCR0_ADDR
#define BN0_WF_LPON_TOP_NANCR0_NAN_BAND_EN_SEL_MASK            0x00000003                // NAN_BAND_EN_SEL[1..0]
#define BN0_WF_LPON_TOP_NANCR0_NAN_BAND_EN_SEL_SHFT            0

/* =====================================================================================

  ---NANCR1 (0x820EB000 + 0x208)---

    NAN_t3_CNT[9..0]             - (RW) This field indicates the NAN t3 value (unit 32 us)
    RESERVED10[15..10]           - (RO) Reserved bits
    NAN_BCN_HC_CNT[25..16]       - (RW) This field indicates the HC value  (unit 32us) .
                                     Software can assign the delay time for Low Power to delay the BCN send time
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_NANCR1_NAN_BCN_HC_CNT_ADDR             BN0_WF_LPON_TOP_NANCR1_ADDR
#define BN0_WF_LPON_TOP_NANCR1_NAN_BCN_HC_CNT_MASK             0x03FF0000                // NAN_BCN_HC_CNT[25..16]
#define BN0_WF_LPON_TOP_NANCR1_NAN_BCN_HC_CNT_SHFT             16
#define BN0_WF_LPON_TOP_NANCR1_NAN_t3_CNT_ADDR                 BN0_WF_LPON_TOP_NANCR1_ADDR
#define BN0_WF_LPON_TOP_NANCR1_NAN_t3_CNT_MASK                 0x000003FF                // NAN_t3_CNT[9..0]
#define BN0_WF_LPON_TOP_NANCR1_NAN_t3_CNT_SHFT                 0

/* =====================================================================================

  ---NANCR2 (0x820EB000 + 0x20c)---

    NAN_TSF_DRIFT_CNT[15..0]     - (RW) This field indicate TSF Drift counter with 2's complement.
                                     Postive means udated TSF is larger than local TSF.
                                     Negative means updated TSF is smaller than local TSF.
    NAN_TSF_DRIFT_EN[16]         - (RW) Enable the Drift counter function.
                                     For 11AX WiFi dual MAC architecture, we have separate TSF for band 0 and band 1. But for the NAN protocol requirement, TSF should be sync between 2G/5G with the same NAN cluster. We use the TSF drift accumulate counter to sync dual MAC TSF by SW.
                                     For NAN usage, we use pre TBTT or pre TTTT interrupt before discovery window to inform SW to prepare some packets, also we can use them to sync TSF. But we must be careful to check  TSF drift counter and pre TBTT interval quantity. We need to prevent TSF sync jump over DW start, because HW need local TSF count through DW start to maintain DW.
    NAN_TSF_DRIFT_OVFL_INT_EN[17] - (RW) Enable the interrupt function by TSF drift counter overflow.
    NAN_TSF_DRIFT_WLANID[19..18] - (RW) We can set NAN operation with each BSS in PRD(4 BSS). We should set the TSF drift counter base to the same BSS to sync the TSF between dual MAC architecture.
                                     2'b00 : BSS 0
                                     2'b01 : BSS 1
                                     2'b10 : BSS 2
                                     2'b11 : BSS 3
    NAN_TSF_DRIFT_RST[20]        - (WO) Write 1 to reset NAN_TSF_DRIFT_CNT
    RESERVED21[31..21]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_NANCR2_NAN_TSF_DRIFT_RST_ADDR          BN0_WF_LPON_TOP_NANCR2_ADDR
#define BN0_WF_LPON_TOP_NANCR2_NAN_TSF_DRIFT_RST_MASK          0x00100000                // NAN_TSF_DRIFT_RST[20]
#define BN0_WF_LPON_TOP_NANCR2_NAN_TSF_DRIFT_RST_SHFT          20
#define BN0_WF_LPON_TOP_NANCR2_NAN_TSF_DRIFT_WLANID_ADDR       BN0_WF_LPON_TOP_NANCR2_ADDR
#define BN0_WF_LPON_TOP_NANCR2_NAN_TSF_DRIFT_WLANID_MASK       0x000C0000                // NAN_TSF_DRIFT_WLANID[19..18]
#define BN0_WF_LPON_TOP_NANCR2_NAN_TSF_DRIFT_WLANID_SHFT       18
#define BN0_WF_LPON_TOP_NANCR2_NAN_TSF_DRIFT_OVFL_INT_EN_ADDR  BN0_WF_LPON_TOP_NANCR2_ADDR
#define BN0_WF_LPON_TOP_NANCR2_NAN_TSF_DRIFT_OVFL_INT_EN_MASK  0x00020000                // NAN_TSF_DRIFT_OVFL_INT_EN[17]
#define BN0_WF_LPON_TOP_NANCR2_NAN_TSF_DRIFT_OVFL_INT_EN_SHFT  17
#define BN0_WF_LPON_TOP_NANCR2_NAN_TSF_DRIFT_EN_ADDR           BN0_WF_LPON_TOP_NANCR2_ADDR
#define BN0_WF_LPON_TOP_NANCR2_NAN_TSF_DRIFT_EN_MASK           0x00010000                // NAN_TSF_DRIFT_EN[16]
#define BN0_WF_LPON_TOP_NANCR2_NAN_TSF_DRIFT_EN_SHFT           16
#define BN0_WF_LPON_TOP_NANCR2_NAN_TSF_DRIFT_CNT_ADDR          BN0_WF_LPON_TOP_NANCR2_ADDR
#define BN0_WF_LPON_TOP_NANCR2_NAN_TSF_DRIFT_CNT_MASK          0x0000FFFF                // NAN_TSF_DRIFT_CNT[15..0]
#define BN0_WF_LPON_TOP_NANCR2_NAN_TSF_DRIFT_CNT_SHFT          0

/* =====================================================================================

  ---AUDIO0 (0x820EB000 + 0x210)---

    TSF_AUDIO_EN[0]              - (RW) This field indicates the enable signal for the function : 
                                     1. Generate an internal TSF timer interrupt signal to AUDIO consys , the pulase width would be 2us.
                                     2. Latch the Local TSF with 64bits to AUDIO consys.
                                     On the other hand . For power saving , we suggest to align the TSF timer and the TBTT timer.
    TSF_AUDIO_LOCAL_TIMER_ID[2..1] - (RW) set 2'h0 ~ 2'h3 to select the local BSSID for tsf timer.
    TSF_AUDIO_SEL[5..3]          - (RW) set 3'h0 ~ 3'h7 to choose the tsf timer t0 ~ t7
    RESERVED6[31..6]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_AUDIO0_TSF_AUDIO_SEL_ADDR              BN0_WF_LPON_TOP_AUDIO0_ADDR
#define BN0_WF_LPON_TOP_AUDIO0_TSF_AUDIO_SEL_MASK              0x00000038                // TSF_AUDIO_SEL[5..3]
#define BN0_WF_LPON_TOP_AUDIO0_TSF_AUDIO_SEL_SHFT              3
#define BN0_WF_LPON_TOP_AUDIO0_TSF_AUDIO_LOCAL_TIMER_ID_ADDR   BN0_WF_LPON_TOP_AUDIO0_ADDR
#define BN0_WF_LPON_TOP_AUDIO0_TSF_AUDIO_LOCAL_TIMER_ID_MASK   0x00000006                // TSF_AUDIO_LOCAL_TIMER_ID[2..1]
#define BN0_WF_LPON_TOP_AUDIO0_TSF_AUDIO_LOCAL_TIMER_ID_SHFT   1
#define BN0_WF_LPON_TOP_AUDIO0_TSF_AUDIO_EN_ADDR               BN0_WF_LPON_TOP_AUDIO0_ADDR
#define BN0_WF_LPON_TOP_AUDIO0_TSF_AUDIO_EN_MASK               0x00000001                // TSF_AUDIO_EN[0]
#define BN0_WF_LPON_TOP_AUDIO0_TSF_AUDIO_EN_SHFT               0

/* =====================================================================================

  ---AUDIO1 (0x820EB000 + 0x214)---

    TSF_LATCH_31_0[31..0]        - (RW) This field indicates the latched value from the 64bits tsf. The value bits is 31~0. 
                                     (It is mainly used for CMDBT backup/restore usage)

 =====================================================================================*/
#define BN0_WF_LPON_TOP_AUDIO1_TSF_LATCH_31_0_ADDR             BN0_WF_LPON_TOP_AUDIO1_ADDR
#define BN0_WF_LPON_TOP_AUDIO1_TSF_LATCH_31_0_MASK             0xFFFFFFFF                // TSF_LATCH_31_0[31..0]
#define BN0_WF_LPON_TOP_AUDIO1_TSF_LATCH_31_0_SHFT             0

/* =====================================================================================

  ---AUDIO2 (0x820EB000 + 0x218)---

    TSF_LATCH_63_32[31..0]       - (RW) This field indicates the latched value from the 64bits tsf. The value bits is 63~32. 
                                     (It is mainly used for CMDBT backup/restore usage)

 =====================================================================================*/
#define BN0_WF_LPON_TOP_AUDIO2_TSF_LATCH_63_32_ADDR            BN0_WF_LPON_TOP_AUDIO2_ADDR
#define BN0_WF_LPON_TOP_AUDIO2_TSF_LATCH_63_32_MASK            0xFFFFFFFF                // TSF_LATCH_63_32[31..0]
#define BN0_WF_LPON_TOP_AUDIO2_TSF_LATCH_63_32_SHFT            0

/* =====================================================================================

  ---TRAPUMAC (0x820EB000 + 0x21c)---

    TX_BSS0_TRAP_UMAC_VAL[0]     - (RU) This field indicates the control value . When trap interrupt occurs , this value will latch into the real control signal to control UMAC BSSID 0.
                                     (It is mainly used for CMDBT backup/restore usage. This register is READ ONLY.)
    TX_BSS1_TRAP_UMAC_VAL[1]     - (RU) This field indicates the control value . When trap interrupt occurs , this value will latch into the real control signal to control UMAC BSSID 1.
                                     (It is mainly used for CMDBT backup/restore usage. This register is READ ONLY.)
    TX_BSS2_TRAP_UMAC_VAL[2]     - (RU) This field indicates the control value . When trap interrupt occurs , this value will latch into the real control signal to control UMAC BSSID 2.
                                     (It is mainly used for CMDBT backup/restore usage. This register is READ ONLY.)
    TX_BSS3_TRAP_UMAC_VAL[3]     - (RU) This field indicates the control value . When trap interrupt occurs , this value will latch into the real control signal to control UMAC BSSID 3.
                                     (It is mainly used for CMDBT backup/restore usage. This register is READ ONLY.)
    RESERVED4[15..4]             - (RO) Reserved bits
    TX_BSS0_TRAP_UMAC_CTL[16]    - (RW) This field indicates the real control signal for traping UMAC BSSID 0 , we can use this field to evaluate the UMAC trap function as follow :
                                     1. Check this bit to know the default status of trap behavior for UMAC BSSID 0.
                                     2. Write this bit with 1'b1 to trap the UMAC BSSID 0 immediately , but this method is not recommened.
                                     3. This bit will become 1'b1 when "trap timer 0 interrupt & (TX_BSS0_TRAP_UMAC_VAL equal = 1'b1) ".
                                     (It is mainly used for CMDBT backup/restore usage)
    TX_BSS1_TRAP_UMAC_CTL[17]    - (RW) This field indicates the real control signal for traping UMAC BSSID 1 , we can use this field to evaluate the UMAC trap function as follow :
                                     1. Check this bit to know the default status of trap behavior for UMAC BSSID 1.
                                     2. Write this bit with 1'b1 to trap the UMAC BSSID 1 immediately , but this method is not recommened.
                                     3. This bit will become 1'b1 when "trap timer 1 interrupt & (TX_BSS1_TRAP_UMAC_VAL equal = 1'b1) ".
                                     (It is mainly used for CMDBT backup/restore usage)
    TX_BSS2_TRAP_UMAC_CTL[18]    - (RW) This field indicates the real control signal for traping UMAC BSSID 2 , we can use this field to evaluate the UMAC trap function as follow :
                                     1. Check this bit to know the default status of trap behavior for UMAC BSSID 2.
                                     2. Write this bit with 1'b1 to trap the UMAC BSSID 2 immediately , but this method is not recommened.
                                     3. This bit will become 1'b1 when "trap timer 2 interrupt & (TX_BSS2_TRAP_UMAC_VAL equal = 1'b1) ".
                                     (It is mainly used for CMDBT backup/restore usage)
    TX_BSS3_TRAP_UMAC_CTL[19]    - (RW) This field indicates the real control signal for traping UMAC BSSID 3 , we can use this field to evaluate the UMAC trap function as follow :
                                     1. Check this bit to know the default status of trap behavior for UMAC BSSID 3.
                                     2. Write this bit with 1'b1 to trap the UMAC BSSID 3 immediately , but this method is not recommened.
                                     3. This bit will become 1'b1 when "trap timer 3 interrupt & (TX_BSS3_TRAP_UMAC_VAL equal = 1'b1) ".
                                     (It is mainly used for CMDBT backup/restore usage)
    RESERVED20[31..20]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS3_TRAP_UMAC_CTL_ADDR    BN0_WF_LPON_TOP_TRAPUMAC_ADDR
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS3_TRAP_UMAC_CTL_MASK    0x00080000                // TX_BSS3_TRAP_UMAC_CTL[19]
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS3_TRAP_UMAC_CTL_SHFT    19
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS2_TRAP_UMAC_CTL_ADDR    BN0_WF_LPON_TOP_TRAPUMAC_ADDR
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS2_TRAP_UMAC_CTL_MASK    0x00040000                // TX_BSS2_TRAP_UMAC_CTL[18]
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS2_TRAP_UMAC_CTL_SHFT    18
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS1_TRAP_UMAC_CTL_ADDR    BN0_WF_LPON_TOP_TRAPUMAC_ADDR
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS1_TRAP_UMAC_CTL_MASK    0x00020000                // TX_BSS1_TRAP_UMAC_CTL[17]
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS1_TRAP_UMAC_CTL_SHFT    17
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS0_TRAP_UMAC_CTL_ADDR    BN0_WF_LPON_TOP_TRAPUMAC_ADDR
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS0_TRAP_UMAC_CTL_MASK    0x00010000                // TX_BSS0_TRAP_UMAC_CTL[16]
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS0_TRAP_UMAC_CTL_SHFT    16
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS3_TRAP_UMAC_VAL_ADDR    BN0_WF_LPON_TOP_TRAPUMAC_ADDR
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS3_TRAP_UMAC_VAL_MASK    0x00000008                // TX_BSS3_TRAP_UMAC_VAL[3]
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS3_TRAP_UMAC_VAL_SHFT    3
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS2_TRAP_UMAC_VAL_ADDR    BN0_WF_LPON_TOP_TRAPUMAC_ADDR
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS2_TRAP_UMAC_VAL_MASK    0x00000004                // TX_BSS2_TRAP_UMAC_VAL[2]
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS2_TRAP_UMAC_VAL_SHFT    2
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS1_TRAP_UMAC_VAL_ADDR    BN0_WF_LPON_TOP_TRAPUMAC_ADDR
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS1_TRAP_UMAC_VAL_MASK    0x00000002                // TX_BSS1_TRAP_UMAC_VAL[1]
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS1_TRAP_UMAC_VAL_SHFT    1
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS0_TRAP_UMAC_VAL_ADDR    BN0_WF_LPON_TOP_TRAPUMAC_ADDR
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS0_TRAP_UMAC_VAL_MASK    0x00000001                // TX_BSS0_TRAP_UMAC_VAL[0]
#define BN0_WF_LPON_TOP_TRAPUMAC_TX_BSS0_TRAP_UMAC_VAL_SHFT    0

/* =====================================================================================

  ---TRAPUMAC_DIS (0x820EB000 + 0x220)---

    RESERVED0[15..0]             - (RO) Reserved bits
    TX_BSS0_TRAP_UMAC_DIS[16]    - (WO) disable UMAC trap control for BSSID 0 , set 1'b1 to disable "TRAP UMAC Register - TX_BSS0_TRAP_UMAC_CTL"
    TX_BSS1_TRAP_UMAC_DIS[17]    - (WO) disable UMAC trap control for BSSID 1 , set 1'b1 to disable "TRAP UMAC Register - TX_BSS1_TRAP_UMAC_CTL"
    TX_BSS2_TRAP_UMAC_DIS[18]    - (WO) disable UMAC trap control for BSSID 2 , set 1'b1 to disable "TRAP UMAC Register - TX_BSS2_TRAP_UMAC_CTL"
    TX_BSS3_TRAP_UMAC_DIS[19]    - (WO) disable UMAC trap control for BSSID 3 , set 1'b1 to disable "TRAP UMAC Register - TX_BSS3_TRAP_UMAC_CTL"
    RESERVED20[31..20]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TRAPUMAC_DIS_TX_BSS3_TRAP_UMAC_DIS_ADDR BN0_WF_LPON_TOP_TRAPUMAC_DIS_ADDR
#define BN0_WF_LPON_TOP_TRAPUMAC_DIS_TX_BSS3_TRAP_UMAC_DIS_MASK 0x00080000                // TX_BSS3_TRAP_UMAC_DIS[19]
#define BN0_WF_LPON_TOP_TRAPUMAC_DIS_TX_BSS3_TRAP_UMAC_DIS_SHFT 19
#define BN0_WF_LPON_TOP_TRAPUMAC_DIS_TX_BSS2_TRAP_UMAC_DIS_ADDR BN0_WF_LPON_TOP_TRAPUMAC_DIS_ADDR
#define BN0_WF_LPON_TOP_TRAPUMAC_DIS_TX_BSS2_TRAP_UMAC_DIS_MASK 0x00040000                // TX_BSS2_TRAP_UMAC_DIS[18]
#define BN0_WF_LPON_TOP_TRAPUMAC_DIS_TX_BSS2_TRAP_UMAC_DIS_SHFT 18
#define BN0_WF_LPON_TOP_TRAPUMAC_DIS_TX_BSS1_TRAP_UMAC_DIS_ADDR BN0_WF_LPON_TOP_TRAPUMAC_DIS_ADDR
#define BN0_WF_LPON_TOP_TRAPUMAC_DIS_TX_BSS1_TRAP_UMAC_DIS_MASK 0x00020000                // TX_BSS1_TRAP_UMAC_DIS[17]
#define BN0_WF_LPON_TOP_TRAPUMAC_DIS_TX_BSS1_TRAP_UMAC_DIS_SHFT 17
#define BN0_WF_LPON_TOP_TRAPUMAC_DIS_TX_BSS0_TRAP_UMAC_DIS_ADDR BN0_WF_LPON_TOP_TRAPUMAC_DIS_ADDR
#define BN0_WF_LPON_TOP_TRAPUMAC_DIS_TX_BSS0_TRAP_UMAC_DIS_MASK 0x00010000                // TX_BSS0_TRAP_UMAC_DIS[16]
#define BN0_WF_LPON_TOP_TRAPUMAC_DIS_TX_BSS0_TRAP_UMAC_DIS_SHFT 16

/* =====================================================================================

  ---NEXT_TRAPUMAC (0x820EB000 + 0x224)---

    TX_BSS0_TRAP_UMAC_VAL[0]     - (RW) This field indicates the control value . When trap interrupt occurs , this value will latch into the real control signal to control UMAC BSSID 0.
                                     (It is mainly used for CMDBT backup/restore usage)
    TX_BSS1_TRAP_UMAC_VAL[1]     - (RW) This field indicates the control value . When trap interrupt occurs , this value will latch into the real control signal to control UMAC BSSID 1.
                                     (It is mainly used for CMDBT backup/restore usage)
    TX_BSS2_TRAP_UMAC_VAL[2]     - (RW) This field indicates the control value . When trap interrupt occurs , this value will latch into the real control signal to control UMAC BSSID 2.
                                     (It is mainly used for CMDBT backup/restore usage)
    TX_BSS3_TRAP_UMAC_VAL[3]     - (RW) This field indicates the control value . When trap interrupt occurs , this value will latch into the real control signal to control UMAC BSSID 3.
                                     (It is mainly used for CMDBT backup/restore usage)
    RESERVED4[31..4]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_NEXT_TRAPUMAC_TX_BSS3_TRAP_UMAC_VAL_ADDR BN0_WF_LPON_TOP_NEXT_TRAPUMAC_ADDR
#define BN0_WF_LPON_TOP_NEXT_TRAPUMAC_TX_BSS3_TRAP_UMAC_VAL_MASK 0x00000008                // TX_BSS3_TRAP_UMAC_VAL[3]
#define BN0_WF_LPON_TOP_NEXT_TRAPUMAC_TX_BSS3_TRAP_UMAC_VAL_SHFT 3
#define BN0_WF_LPON_TOP_NEXT_TRAPUMAC_TX_BSS2_TRAP_UMAC_VAL_ADDR BN0_WF_LPON_TOP_NEXT_TRAPUMAC_ADDR
#define BN0_WF_LPON_TOP_NEXT_TRAPUMAC_TX_BSS2_TRAP_UMAC_VAL_MASK 0x00000004                // TX_BSS2_TRAP_UMAC_VAL[2]
#define BN0_WF_LPON_TOP_NEXT_TRAPUMAC_TX_BSS2_TRAP_UMAC_VAL_SHFT 2
#define BN0_WF_LPON_TOP_NEXT_TRAPUMAC_TX_BSS1_TRAP_UMAC_VAL_ADDR BN0_WF_LPON_TOP_NEXT_TRAPUMAC_ADDR
#define BN0_WF_LPON_TOP_NEXT_TRAPUMAC_TX_BSS1_TRAP_UMAC_VAL_MASK 0x00000002                // TX_BSS1_TRAP_UMAC_VAL[1]
#define BN0_WF_LPON_TOP_NEXT_TRAPUMAC_TX_BSS1_TRAP_UMAC_VAL_SHFT 1
#define BN0_WF_LPON_TOP_NEXT_TRAPUMAC_TX_BSS0_TRAP_UMAC_VAL_ADDR BN0_WF_LPON_TOP_NEXT_TRAPUMAC_ADDR
#define BN0_WF_LPON_TOP_NEXT_TRAPUMAC_TX_BSS0_TRAP_UMAC_VAL_MASK 0x00000001                // TX_BSS0_TRAP_UMAC_VAL[0]
#define BN0_WF_LPON_TOP_NEXT_TRAPUMAC_TX_BSS0_TRAP_UMAC_VAL_SHFT 0

/* =====================================================================================

  ---CGFIX (0x820EB000 + 0x228)---

    CG_RESTORE_QUIET_EN[0]       - (RW) Disable clocking gating fix of quiet(timer)_en signal.
    CG_RESTORE_MEASUREMENT_EN[1] - (RW) Disable clocking gating fix of measurement(timer)_en signal.
    RESERVED[31..2]              - (RW) Reserved

 =====================================================================================*/
#define BN0_WF_LPON_TOP_CGFIX_CG_RESTORE_MEASUREMENT_EN_ADDR   BN0_WF_LPON_TOP_CGFIX_ADDR
#define BN0_WF_LPON_TOP_CGFIX_CG_RESTORE_MEASUREMENT_EN_MASK   0x00000002                // CG_RESTORE_MEASUREMENT_EN[1]
#define BN0_WF_LPON_TOP_CGFIX_CG_RESTORE_MEASUREMENT_EN_SHFT   1
#define BN0_WF_LPON_TOP_CGFIX_CG_RESTORE_QUIET_EN_ADDR         BN0_WF_LPON_TOP_CGFIX_ADDR
#define BN0_WF_LPON_TOP_CGFIX_CG_RESTORE_QUIET_EN_MASK         0x00000001                // CG_RESTORE_QUIET_EN[0]
#define BN0_WF_LPON_TOP_CGFIX_CG_RESTORE_QUIET_EN_SHFT         0

/* =====================================================================================

  ---PHYOUTCR (0x820EB000 + 0x22c)---

    LP_CR_BCN_POUT_ENABLE[0]     - (RW) 0: Disable the phyout mtcmos trigger source from beacon service period rising
                                     1: Enable the phyout mtcmos trigger source from beacon service period rising
    LP_CR_BMC_POUT_ENABLE[1]     - (RW) 0: Disable the phyout mtcmos trigger source from bmc service period rising
                                     1: Enable the phyout mtcmos trigger source from bmc service period rising
    LP_CR_TIM_POUT_ENABLE[2]     - (RW) 0: Disable the phyout mtcmos trigger source from tim_broadcast service period rising
                                     1: Enable the phyout mtcmos trigger source from tim_broadcast service period rising
    LP_CR_TIM_BMC_POUT_ENABLE[3] - (RW) 0: Disable the phyout mtcmos trigger source from tim_bmc service period rising
                                     1: Enable the phyout mtcmos trigger source from tim_bmc service period rising
    LP_CR_NAN_2P4G_POUT_ENABLE[4] - (RW) 0: Disable the phyout mtcmos trigger source from NAN 2.4G service period rising
                                     1: Enable the phyout mtcmos trigger source from NAN 2.4G service period rising
    LP_CR_NAN_5G_POUT_ENABLE[5]  - (RW) 0: Disable the phyout mtcmos trigger source from NAN 5G service period rising
                                     1: Enable the phyout mtcmos trigger source from NAN 5G service period rising
    LP_CR_BCN_SET_POUT_ENABLE[6] - (RW) 0: Disable the phyout mtcmos trigger source from beacon received
                                     1: Enable the phyout mtcmos trigger source from beacon received
    LP_CR_TIM_SET_POUT_ENABLE[7] - (RW) 0: Disable the phyout mtcmos trigger source from tim broadcast received
                                     1: Enable the phyout mtcmos trigger source from tim broadcast received
    LP_CR_PARTIAL_BCN_SET_POUT_ENABLE[8] - (RW) 0: Disable the phyout mtcmos trigger source from partial beacon received
                                     1: Enable the phyout mtcmos trigger source from partial beacon received
    RESERVED9[31..9]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_PARTIAL_BCN_SET_POUT_ENABLE_ADDR BN0_WF_LPON_TOP_PHYOUTCR_ADDR
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_PARTIAL_BCN_SET_POUT_ENABLE_MASK 0x00000100                // LP_CR_PARTIAL_BCN_SET_POUT_ENABLE[8]
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_PARTIAL_BCN_SET_POUT_ENABLE_SHFT 8
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_TIM_SET_POUT_ENABLE_ADDR BN0_WF_LPON_TOP_PHYOUTCR_ADDR
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_TIM_SET_POUT_ENABLE_MASK 0x00000080                // LP_CR_TIM_SET_POUT_ENABLE[7]
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_TIM_SET_POUT_ENABLE_SHFT 7
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_BCN_SET_POUT_ENABLE_ADDR BN0_WF_LPON_TOP_PHYOUTCR_ADDR
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_BCN_SET_POUT_ENABLE_MASK 0x00000040                // LP_CR_BCN_SET_POUT_ENABLE[6]
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_BCN_SET_POUT_ENABLE_SHFT 6
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_NAN_5G_POUT_ENABLE_ADDR BN0_WF_LPON_TOP_PHYOUTCR_ADDR
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_NAN_5G_POUT_ENABLE_MASK 0x00000020                // LP_CR_NAN_5G_POUT_ENABLE[5]
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_NAN_5G_POUT_ENABLE_SHFT 5
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_NAN_2P4G_POUT_ENABLE_ADDR BN0_WF_LPON_TOP_PHYOUTCR_ADDR
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_NAN_2P4G_POUT_ENABLE_MASK 0x00000010                // LP_CR_NAN_2P4G_POUT_ENABLE[4]
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_NAN_2P4G_POUT_ENABLE_SHFT 4
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_TIM_BMC_POUT_ENABLE_ADDR BN0_WF_LPON_TOP_PHYOUTCR_ADDR
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_TIM_BMC_POUT_ENABLE_MASK 0x00000008                // LP_CR_TIM_BMC_POUT_ENABLE[3]
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_TIM_BMC_POUT_ENABLE_SHFT 3
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_TIM_POUT_ENABLE_ADDR    BN0_WF_LPON_TOP_PHYOUTCR_ADDR
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_TIM_POUT_ENABLE_MASK    0x00000004                // LP_CR_TIM_POUT_ENABLE[2]
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_TIM_POUT_ENABLE_SHFT    2
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_BMC_POUT_ENABLE_ADDR    BN0_WF_LPON_TOP_PHYOUTCR_ADDR
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_BMC_POUT_ENABLE_MASK    0x00000002                // LP_CR_BMC_POUT_ENABLE[1]
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_BMC_POUT_ENABLE_SHFT    1
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_BCN_POUT_ENABLE_ADDR    BN0_WF_LPON_TOP_PHYOUTCR_ADDR
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_BCN_POUT_ENABLE_MASK    0x00000001                // LP_CR_BCN_POUT_ENABLE[0]
#define BN0_WF_LPON_TOP_PHYOUTCR_LP_CR_BCN_POUT_ENABLE_SHFT    0

/* =====================================================================================

  ---TWT0CR (0x820EB000 + 0x230)---

    LOCAL_TSF_TIMER_ID[1..0]     - (RW) Controls which tsf(tsf0-3,associated to bssid0-3) to be referenced for the timer.
    PERIODIC_MODE[2]             - (RW) Controls period_mode used for TWT timer 
                                     0: Start time
                                     1: Period (If PERIOD_MODE is 0 when this value is set, it will be a one-shot timer; otherwise, it will be an auto-repeat timer.)
    LP_CR_TWT0_NO_DRIFT_CHK[3]   - (RW) Controls drift window protection use with TWT_DRIFT_WIN.
                                     1: Disable drift window protection. Once twt timer behind tsf when jumping and instant check, twt interrupt will assert .
                                     0: Enable drift window protection. Once twt timer behind tsf when jumping and instant checking, twt interrupt will assert  by drift situation.
    RESERVED4[31..4]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TWT0CR_LP_CR_TWT0_NO_DRIFT_CHK_ADDR    BN0_WF_LPON_TOP_TWT0CR_ADDR
#define BN0_WF_LPON_TOP_TWT0CR_LP_CR_TWT0_NO_DRIFT_CHK_MASK    0x00000008                // LP_CR_TWT0_NO_DRIFT_CHK[3]
#define BN0_WF_LPON_TOP_TWT0CR_LP_CR_TWT0_NO_DRIFT_CHK_SHFT    3
#define BN0_WF_LPON_TOP_TWT0CR_PERIODIC_MODE_ADDR              BN0_WF_LPON_TOP_TWT0CR_ADDR
#define BN0_WF_LPON_TOP_TWT0CR_PERIODIC_MODE_MASK              0x00000004                // PERIODIC_MODE[2]
#define BN0_WF_LPON_TOP_TWT0CR_PERIODIC_MODE_SHFT              2
#define BN0_WF_LPON_TOP_TWT0CR_LOCAL_TSF_TIMER_ID_ADDR         BN0_WF_LPON_TOP_TWT0CR_ADDR
#define BN0_WF_LPON_TOP_TWT0CR_LOCAL_TSF_TIMER_ID_MASK         0x00000003                // LOCAL_TSF_TIMER_ID[1..0]
#define BN0_WF_LPON_TOP_TWT0CR_LOCAL_TSF_TIMER_ID_SHFT         0

/* =====================================================================================

  ---TWT1CR (0x820EB000 + 0x234)---

    LOCAL_TSF_TIMER_ID[1..0]     - (RW) Controls which tsf(tsf0-3,associated to bssid0-3) to be referenced for the timer.
    PERIODIC_MODE[2]             - (RW) Controls time_value used for T0 timer 
                                     0: Start time
                                     1: Period (If TIME_VALUE is 0 when this value is set, it will be a one-shot timer; otherwise, it will be an auto-repeat timer.)
    LP_CR_TWT1_NO_DRIFT_CHK[3]   - (RW) Controls drift window protection use with TWT_DRIFT_WIN.
                                     1: Disable drift window protection. Once twt timer behind tsf when jumping and instant check, twt interrupt will assert .
                                     0: Enable drift window protection. Once twt timer behind tsf when jumping and instant checking, twt interrupt will assert  by drift situation.
    RESERVED4[31..4]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TWT1CR_LP_CR_TWT1_NO_DRIFT_CHK_ADDR    BN0_WF_LPON_TOP_TWT1CR_ADDR
#define BN0_WF_LPON_TOP_TWT1CR_LP_CR_TWT1_NO_DRIFT_CHK_MASK    0x00000008                // LP_CR_TWT1_NO_DRIFT_CHK[3]
#define BN0_WF_LPON_TOP_TWT1CR_LP_CR_TWT1_NO_DRIFT_CHK_SHFT    3
#define BN0_WF_LPON_TOP_TWT1CR_PERIODIC_MODE_ADDR              BN0_WF_LPON_TOP_TWT1CR_ADDR
#define BN0_WF_LPON_TOP_TWT1CR_PERIODIC_MODE_MASK              0x00000004                // PERIODIC_MODE[2]
#define BN0_WF_LPON_TOP_TWT1CR_PERIODIC_MODE_SHFT              2
#define BN0_WF_LPON_TOP_TWT1CR_LOCAL_TSF_TIMER_ID_ADDR         BN0_WF_LPON_TOP_TWT1CR_ADDR
#define BN0_WF_LPON_TOP_TWT1CR_LOCAL_TSF_TIMER_ID_MASK         0x00000003                // LOCAL_TSF_TIMER_ID[1..0]
#define BN0_WF_LPON_TOP_TWT1CR_LOCAL_TSF_TIMER_ID_SHFT         0

/* =====================================================================================

  ---TWT0VR0 (0x820EB000 + 0x238)---

    TWT_TIMER_VALUE_L[31..0]     - (RW) twt timer count value LSB 31_0
                                     Unit: 1us

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TWT0VR0_TWT_TIMER_VALUE_L_ADDR         BN0_WF_LPON_TOP_TWT0VR0_ADDR
#define BN0_WF_LPON_TOP_TWT0VR0_TWT_TIMER_VALUE_L_MASK         0xFFFFFFFF                // TWT_TIMER_VALUE_L[31..0]
#define BN0_WF_LPON_TOP_TWT0VR0_TWT_TIMER_VALUE_L_SHFT         0

/* =====================================================================================

  ---TWT0VR1 (0x820EB000 + 0x23c)---

    TWT_TIMER_VALUE_H[31..0]     - (RW) twt timer count value MSB 63_32
                                     Unit: 1us

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TWT0VR1_TWT_TIMER_VALUE_H_ADDR         BN0_WF_LPON_TOP_TWT0VR1_ADDR
#define BN0_WF_LPON_TOP_TWT0VR1_TWT_TIMER_VALUE_H_MASK         0xFFFFFFFF                // TWT_TIMER_VALUE_H[31..0]
#define BN0_WF_LPON_TOP_TWT0VR1_TWT_TIMER_VALUE_H_SHFT         0

/* =====================================================================================

  ---TWT1VR0 (0x820EB000 + 0x240)---

    TWT_TIMER_VALUE_L[31..0]     - (RW) twt timer count value LSB 31_0
                                     Unit: 1us

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TWT1VR0_TWT_TIMER_VALUE_L_ADDR         BN0_WF_LPON_TOP_TWT1VR0_ADDR
#define BN0_WF_LPON_TOP_TWT1VR0_TWT_TIMER_VALUE_L_MASK         0xFFFFFFFF                // TWT_TIMER_VALUE_L[31..0]
#define BN0_WF_LPON_TOP_TWT1VR0_TWT_TIMER_VALUE_L_SHFT         0

/* =====================================================================================

  ---TWT1VR1 (0x820EB000 + 0x244)---

    TWT_TIMER_VALUE_H[31..0]     - (RW) twt timer count value MSB 63_32
                                     Unit: 1us

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TWT1VR1_TWT_TIMER_VALUE_H_ADDR         BN0_WF_LPON_TOP_TWT1VR1_ADDR
#define BN0_WF_LPON_TOP_TWT1VR1_TWT_TIMER_VALUE_H_MASK         0xFFFFFFFF                // TWT_TIMER_VALUE_H[31..0]
#define BN0_WF_LPON_TOP_TWT1VR1_TWT_TIMER_VALUE_H_SHFT         0

/* =====================================================================================

  ---TWT0TR0 (0x820EB000 + 0x248)---

    LP_TAR_TWT_TIMER_L[31..0]    - (RW) HW local TWT timer 0 target value LSB 31_0
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TWT0TR0_LP_TAR_TWT_TIMER_L_ADDR        BN0_WF_LPON_TOP_TWT0TR0_ADDR
#define BN0_WF_LPON_TOP_TWT0TR0_LP_TAR_TWT_TIMER_L_MASK        0xFFFFFFFF                // LP_TAR_TWT_TIMER_L[31..0]
#define BN0_WF_LPON_TOP_TWT0TR0_LP_TAR_TWT_TIMER_L_SHFT        0

/* =====================================================================================

  ---TWT0TR1 (0x820EB000 + 0x24c)---

    LP_TAR_TWT_TIMER_H[31..0]    - (RW) HW local TWT timer 0 target value MSB 63_32
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TWT0TR1_LP_TAR_TWT_TIMER_H_ADDR        BN0_WF_LPON_TOP_TWT0TR1_ADDR
#define BN0_WF_LPON_TOP_TWT0TR1_LP_TAR_TWT_TIMER_H_MASK        0xFFFFFFFF                // LP_TAR_TWT_TIMER_H[31..0]
#define BN0_WF_LPON_TOP_TWT0TR1_LP_TAR_TWT_TIMER_H_SHFT        0

/* =====================================================================================

  ---TWT1TR0 (0x820EB000 + 0x250)---

    LP_TAR_TWT_TIMER_L[31..0]    - (RW) HW local TWT timer 1 target value LSB 31_0
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TWT1TR0_LP_TAR_TWT_TIMER_L_ADDR        BN0_WF_LPON_TOP_TWT1TR0_ADDR
#define BN0_WF_LPON_TOP_TWT1TR0_LP_TAR_TWT_TIMER_L_MASK        0xFFFFFFFF                // LP_TAR_TWT_TIMER_L[31..0]
#define BN0_WF_LPON_TOP_TWT1TR0_LP_TAR_TWT_TIMER_L_SHFT        0

/* =====================================================================================

  ---TWT1TR1 (0x820EB000 + 0x254)---

    LP_TAR_TWT_TIMER_H[31..0]    - (RW) HW local TWT timer 1 target value MSB 63_32
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TWT1TR1_LP_TAR_TWT_TIMER_H_ADDR        BN0_WF_LPON_TOP_TWT1TR1_ADDR
#define BN0_WF_LPON_TOP_TWT1TR1_LP_TAR_TWT_TIMER_H_MASK        0xFFFFFFFF                // LP_TAR_TWT_TIMER_H[31..0]
#define BN0_WF_LPON_TOP_TWT1TR1_LP_TAR_TWT_TIMER_H_SHFT        0

/* =====================================================================================

  ---MUEDCA0CR (0x820EB000 + 0x258)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA0CR_MU_EDCA_TIMER_VALUE_ADDR     BN0_WF_LPON_TOP_MUEDCA0CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA0CR_MU_EDCA_TIMER_VALUE_MASK     0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA0CR_MU_EDCA_TIMER_VALUE_SHFT     0

/* =====================================================================================

  ---MUEDCA1CR (0x820EB000 + 0x25c)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA1CR_MU_EDCA_TIMER_VALUE_ADDR     BN0_WF_LPON_TOP_MUEDCA1CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA1CR_MU_EDCA_TIMER_VALUE_MASK     0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA1CR_MU_EDCA_TIMER_VALUE_SHFT     0

/* =====================================================================================

  ---MUEDCA2CR (0x820EB000 + 0x260)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA2CR_MU_EDCA_TIMER_VALUE_ADDR     BN0_WF_LPON_TOP_MUEDCA2CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA2CR_MU_EDCA_TIMER_VALUE_MASK     0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA2CR_MU_EDCA_TIMER_VALUE_SHFT     0

/* =====================================================================================

  ---MUEDCA3CR (0x820EB000 + 0x264)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA3CR_MU_EDCA_TIMER_VALUE_ADDR     BN0_WF_LPON_TOP_MUEDCA3CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA3CR_MU_EDCA_TIMER_VALUE_MASK     0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA3CR_MU_EDCA_TIMER_VALUE_SHFT     0

/* =====================================================================================

  ---MUEDCA4CR (0x820EB000 + 0x268)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA4CR_MU_EDCA_TIMER_VALUE_ADDR     BN0_WF_LPON_TOP_MUEDCA4CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA4CR_MU_EDCA_TIMER_VALUE_MASK     0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA4CR_MU_EDCA_TIMER_VALUE_SHFT     0

/* =====================================================================================

  ---MUEDCA5CR (0x820EB000 + 0x26c)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA5CR_MU_EDCA_TIMER_VALUE_ADDR     BN0_WF_LPON_TOP_MUEDCA5CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA5CR_MU_EDCA_TIMER_VALUE_MASK     0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA5CR_MU_EDCA_TIMER_VALUE_SHFT     0

/* =====================================================================================

  ---MUEDCA6CR (0x820EB000 + 0x270)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA6CR_MU_EDCA_TIMER_VALUE_ADDR     BN0_WF_LPON_TOP_MUEDCA6CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA6CR_MU_EDCA_TIMER_VALUE_MASK     0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA6CR_MU_EDCA_TIMER_VALUE_SHFT     0

/* =====================================================================================

  ---MUEDCA7CR (0x820EB000 + 0x274)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA7CR_MU_EDCA_TIMER_VALUE_ADDR     BN0_WF_LPON_TOP_MUEDCA7CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA7CR_MU_EDCA_TIMER_VALUE_MASK     0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA7CR_MU_EDCA_TIMER_VALUE_SHFT     0

/* =====================================================================================

  ---MUEDCA8CR (0x820EB000 + 0x278)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA8CR_MU_EDCA_TIMER_VALUE_ADDR     BN0_WF_LPON_TOP_MUEDCA8CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA8CR_MU_EDCA_TIMER_VALUE_MASK     0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA8CR_MU_EDCA_TIMER_VALUE_SHFT     0

/* =====================================================================================

  ---MUEDCA9CR (0x820EB000 + 0x27c)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA9CR_MU_EDCA_TIMER_VALUE_ADDR     BN0_WF_LPON_TOP_MUEDCA9CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA9CR_MU_EDCA_TIMER_VALUE_MASK     0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA9CR_MU_EDCA_TIMER_VALUE_SHFT     0

/* =====================================================================================

  ---MUEDCA10CR (0x820EB000 + 0x280)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA10CR_MU_EDCA_TIMER_VALUE_ADDR    BN0_WF_LPON_TOP_MUEDCA10CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA10CR_MU_EDCA_TIMER_VALUE_MASK    0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA10CR_MU_EDCA_TIMER_VALUE_SHFT    0

/* =====================================================================================

  ---MUEDCA11CR (0x820EB000 + 0x284)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA11CR_MU_EDCA_TIMER_VALUE_ADDR    BN0_WF_LPON_TOP_MUEDCA11CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA11CR_MU_EDCA_TIMER_VALUE_MASK    0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA11CR_MU_EDCA_TIMER_VALUE_SHFT    0

/* =====================================================================================

  ---MUEDCA12CR (0x820EB000 + 0x288)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA12CR_MU_EDCA_TIMER_VALUE_ADDR    BN0_WF_LPON_TOP_MUEDCA12CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA12CR_MU_EDCA_TIMER_VALUE_MASK    0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA12CR_MU_EDCA_TIMER_VALUE_SHFT    0

/* =====================================================================================

  ---MUEDCA13CR (0x820EB000 + 0x28c)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA13CR_MU_EDCA_TIMER_VALUE_ADDR    BN0_WF_LPON_TOP_MUEDCA13CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA13CR_MU_EDCA_TIMER_VALUE_MASK    0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA13CR_MU_EDCA_TIMER_VALUE_SHFT    0

/* =====================================================================================

  ---MUEDCA14CR (0x820EB000 + 0x290)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA14CR_MU_EDCA_TIMER_VALUE_ADDR    BN0_WF_LPON_TOP_MUEDCA14CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA14CR_MU_EDCA_TIMER_VALUE_MASK    0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA14CR_MU_EDCA_TIMER_VALUE_SHFT    0

/* =====================================================================================

  ---MUEDCA15CR (0x820EB000 + 0x294)---

    MU_EDCA_TIMER_VALUE[7..0]    - (RW) mu edca timer  value
                                     Unit: 8TU
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA15CR_MU_EDCA_TIMER_VALUE_ADDR    BN0_WF_LPON_TOP_MUEDCA15CR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA15CR_MU_EDCA_TIMER_VALUE_MASK    0x000000FF                // MU_EDCA_TIMER_VALUE[7..0]
#define BN0_WF_LPON_TOP_MUEDCA15CR_MU_EDCA_TIMER_VALUE_SHFT    0

/* =====================================================================================

  ---MUEDCA0TR (0x820EB000 + 0x298)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA0TR_MU_EDCA_FLAG_ADDR            BN0_WF_LPON_TOP_MUEDCA0TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA0TR_MU_EDCA_FLAG_MASK            0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA0TR_MU_EDCA_FLAG_SHFT            31
#define BN0_WF_LPON_TOP_MUEDCA0TR_MU_EDCA_TIMER_ADDR           BN0_WF_LPON_TOP_MUEDCA0TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA0TR_MU_EDCA_TIMER_MASK           0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA0TR_MU_EDCA_TIMER_SHFT           0

/* =====================================================================================

  ---MUEDCA1TR (0x820EB000 + 0x29c)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA1TR_MU_EDCA_FLAG_ADDR            BN0_WF_LPON_TOP_MUEDCA1TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA1TR_MU_EDCA_FLAG_MASK            0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA1TR_MU_EDCA_FLAG_SHFT            31
#define BN0_WF_LPON_TOP_MUEDCA1TR_MU_EDCA_TIMER_ADDR           BN0_WF_LPON_TOP_MUEDCA1TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA1TR_MU_EDCA_TIMER_MASK           0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA1TR_MU_EDCA_TIMER_SHFT           0

/* =====================================================================================

  ---MUEDCA2TR (0x820EB000 + 0x2a0)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA2TR_MU_EDCA_FLAG_ADDR            BN0_WF_LPON_TOP_MUEDCA2TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA2TR_MU_EDCA_FLAG_MASK            0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA2TR_MU_EDCA_FLAG_SHFT            31
#define BN0_WF_LPON_TOP_MUEDCA2TR_MU_EDCA_TIMER_ADDR           BN0_WF_LPON_TOP_MUEDCA2TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA2TR_MU_EDCA_TIMER_MASK           0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA2TR_MU_EDCA_TIMER_SHFT           0

/* =====================================================================================

  ---MUEDCA3TR (0x820EB000 + 0x2a4)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA3TR_MU_EDCA_FLAG_ADDR            BN0_WF_LPON_TOP_MUEDCA3TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA3TR_MU_EDCA_FLAG_MASK            0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA3TR_MU_EDCA_FLAG_SHFT            31
#define BN0_WF_LPON_TOP_MUEDCA3TR_MU_EDCA_TIMER_ADDR           BN0_WF_LPON_TOP_MUEDCA3TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA3TR_MU_EDCA_TIMER_MASK           0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA3TR_MU_EDCA_TIMER_SHFT           0

/* =====================================================================================

  ---MUEDCA4TR (0x820EB000 + 0x2a8)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA4TR_MU_EDCA_FLAG_ADDR            BN0_WF_LPON_TOP_MUEDCA4TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA4TR_MU_EDCA_FLAG_MASK            0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA4TR_MU_EDCA_FLAG_SHFT            31
#define BN0_WF_LPON_TOP_MUEDCA4TR_MU_EDCA_TIMER_ADDR           BN0_WF_LPON_TOP_MUEDCA4TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA4TR_MU_EDCA_TIMER_MASK           0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA4TR_MU_EDCA_TIMER_SHFT           0

/* =====================================================================================

  ---MUEDCA5TR (0x820EB000 + 0x2ac)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA5TR_MU_EDCA_FLAG_ADDR            BN0_WF_LPON_TOP_MUEDCA5TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA5TR_MU_EDCA_FLAG_MASK            0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA5TR_MU_EDCA_FLAG_SHFT            31
#define BN0_WF_LPON_TOP_MUEDCA5TR_MU_EDCA_TIMER_ADDR           BN0_WF_LPON_TOP_MUEDCA5TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA5TR_MU_EDCA_TIMER_MASK           0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA5TR_MU_EDCA_TIMER_SHFT           0

/* =====================================================================================

  ---MUEDCA6TR (0x820EB000 + 0x2b0)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA6TR_MU_EDCA_FLAG_ADDR            BN0_WF_LPON_TOP_MUEDCA6TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA6TR_MU_EDCA_FLAG_MASK            0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA6TR_MU_EDCA_FLAG_SHFT            31
#define BN0_WF_LPON_TOP_MUEDCA6TR_MU_EDCA_TIMER_ADDR           BN0_WF_LPON_TOP_MUEDCA6TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA6TR_MU_EDCA_TIMER_MASK           0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA6TR_MU_EDCA_TIMER_SHFT           0

/* =====================================================================================

  ---MUEDCA7TR (0x820EB000 + 0x2b4)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA7TR_MU_EDCA_FLAG_ADDR            BN0_WF_LPON_TOP_MUEDCA7TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA7TR_MU_EDCA_FLAG_MASK            0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA7TR_MU_EDCA_FLAG_SHFT            31
#define BN0_WF_LPON_TOP_MUEDCA7TR_MU_EDCA_TIMER_ADDR           BN0_WF_LPON_TOP_MUEDCA7TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA7TR_MU_EDCA_TIMER_MASK           0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA7TR_MU_EDCA_TIMER_SHFT           0

/* =====================================================================================

  ---MUEDCA8TR (0x820EB000 + 0x2b8)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA8TR_MU_EDCA_FLAG_ADDR            BN0_WF_LPON_TOP_MUEDCA8TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA8TR_MU_EDCA_FLAG_MASK            0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA8TR_MU_EDCA_FLAG_SHFT            31
#define BN0_WF_LPON_TOP_MUEDCA8TR_MU_EDCA_TIMER_ADDR           BN0_WF_LPON_TOP_MUEDCA8TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA8TR_MU_EDCA_TIMER_MASK           0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA8TR_MU_EDCA_TIMER_SHFT           0

/* =====================================================================================

  ---MUEDCA9TR (0x820EB000 + 0x2bc)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA9TR_MU_EDCA_FLAG_ADDR            BN0_WF_LPON_TOP_MUEDCA9TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA9TR_MU_EDCA_FLAG_MASK            0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA9TR_MU_EDCA_FLAG_SHFT            31
#define BN0_WF_LPON_TOP_MUEDCA9TR_MU_EDCA_TIMER_ADDR           BN0_WF_LPON_TOP_MUEDCA9TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA9TR_MU_EDCA_TIMER_MASK           0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA9TR_MU_EDCA_TIMER_SHFT           0

/* =====================================================================================

  ---MUEDCA10TR (0x820EB000 + 0x2c0)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA10TR_MU_EDCA_FLAG_ADDR           BN0_WF_LPON_TOP_MUEDCA10TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA10TR_MU_EDCA_FLAG_MASK           0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA10TR_MU_EDCA_FLAG_SHFT           31
#define BN0_WF_LPON_TOP_MUEDCA10TR_MU_EDCA_TIMER_ADDR          BN0_WF_LPON_TOP_MUEDCA10TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA10TR_MU_EDCA_TIMER_MASK          0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA10TR_MU_EDCA_TIMER_SHFT          0

/* =====================================================================================

  ---MUEDCA11TR (0x820EB000 + 0x2c4)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA11TR_MU_EDCA_FLAG_ADDR           BN0_WF_LPON_TOP_MUEDCA11TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA11TR_MU_EDCA_FLAG_MASK           0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA11TR_MU_EDCA_FLAG_SHFT           31
#define BN0_WF_LPON_TOP_MUEDCA11TR_MU_EDCA_TIMER_ADDR          BN0_WF_LPON_TOP_MUEDCA11TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA11TR_MU_EDCA_TIMER_MASK          0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA11TR_MU_EDCA_TIMER_SHFT          0

/* =====================================================================================

  ---MUEDCA12TR (0x820EB000 + 0x2c8)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA12TR_MU_EDCA_FLAG_ADDR           BN0_WF_LPON_TOP_MUEDCA12TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA12TR_MU_EDCA_FLAG_MASK           0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA12TR_MU_EDCA_FLAG_SHFT           31
#define BN0_WF_LPON_TOP_MUEDCA12TR_MU_EDCA_TIMER_ADDR          BN0_WF_LPON_TOP_MUEDCA12TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA12TR_MU_EDCA_TIMER_MASK          0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA12TR_MU_EDCA_TIMER_SHFT          0

/* =====================================================================================

  ---MUEDCA13TR (0x820EB000 + 0x2cc)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA13TR_MU_EDCA_FLAG_ADDR           BN0_WF_LPON_TOP_MUEDCA13TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA13TR_MU_EDCA_FLAG_MASK           0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA13TR_MU_EDCA_FLAG_SHFT           31
#define BN0_WF_LPON_TOP_MUEDCA13TR_MU_EDCA_TIMER_ADDR          BN0_WF_LPON_TOP_MUEDCA13TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA13TR_MU_EDCA_TIMER_MASK          0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA13TR_MU_EDCA_TIMER_SHFT          0

/* =====================================================================================

  ---MUEDCA14TR (0x820EB000 + 0x2d0)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA14TR_MU_EDCA_FLAG_ADDR           BN0_WF_LPON_TOP_MUEDCA14TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA14TR_MU_EDCA_FLAG_MASK           0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA14TR_MU_EDCA_FLAG_SHFT           31
#define BN0_WF_LPON_TOP_MUEDCA14TR_MU_EDCA_TIMER_ADDR          BN0_WF_LPON_TOP_MUEDCA14TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA14TR_MU_EDCA_TIMER_MASK          0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA14TR_MU_EDCA_TIMER_SHFT          0

/* =====================================================================================

  ---MUEDCA15TR (0x820EB000 + 0x2d4)---

    MU_EDCA_TIMER[20..0]         - (RW) HW local MU EDCA timer  target value.
                                     Mainly used for CMDBT backup/restore usage.
    RESERVED21[30..21]           - (RO) Reserved bits
    MU_EDCA_FLAG[31]             - (RW) HW local MU EDCA flag.
                                     Mainly used for CMDBT backup/restore usage.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MUEDCA15TR_MU_EDCA_FLAG_ADDR           BN0_WF_LPON_TOP_MUEDCA15TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA15TR_MU_EDCA_FLAG_MASK           0x80000000                // MU_EDCA_FLAG[31]
#define BN0_WF_LPON_TOP_MUEDCA15TR_MU_EDCA_FLAG_SHFT           31
#define BN0_WF_LPON_TOP_MUEDCA15TR_MU_EDCA_TIMER_ADDR          BN0_WF_LPON_TOP_MUEDCA15TR_ADDR
#define BN0_WF_LPON_TOP_MUEDCA15TR_MU_EDCA_TIMER_MASK          0x001FFFFF                // MU_EDCA_TIMER[20..0]
#define BN0_WF_LPON_TOP_MUEDCA15TR_MU_EDCA_TIMER_SHFT          0

/* =====================================================================================

  ---TXTCR0 (0x820EB000 + 0x2d8)---

    TX_TRAP0_TIME_EN[0]          - (RW) Enables TX trap timer
                                     When configuring this timer to be one shot timer, clear this bit at Trap Time.
    TRAP0_PERIOD_ONE_SHOT[1]     - (RO) Trap timer could only be a one-shot timer.
    CEASE_TX_TRAP0[5..2]         - (RW) When this bit is enabled, HW MAC should guarantee two things:
                                     I) The remaining packets transmission time of ACX0~ACX4, (X=0~3) should not exceed the trap time. (The transmission time includes the response time required.)
                                     2) HW should stop ACX0~ACX4 queues.
    CEASE_BCN_TRAP0[6]           - (RW) To preserve the elasticity of the trap configuration, when this bit is enabled, the remaining packets transmission time in BCN queue should not exceed the trap time.
                                     (The transmission time includes the response time required.)
                                     HW should stop BCN queue when the TSF is trapped.
    CEASE_BMC_TRAP0[7]           - (RW) To preserve the elasticity of trap configuration, when this bit is enabled, the remaining packets transmission time in BMC queue should not exceed the trap time.
                                     (The transmission time includes the response time required.)
                                     HW should stop BMC queue when the TSF is trapped.
    CEASE_RWP_TRAP0[8]           - (RW) To preserve the elasticity of trap configuration, when this bit is enabled, the remaining packets transmission time in RWP queue should not exceed the trap time.
                                     (The transmission time includes the response time required.)
                                     HW should stop RWP queue when the TSF is trapped.
    CEASE_ALTX_TRAP0[9]          - (RW) To preserve the elasticity of trap configuration, when this bit is enabled, the remaining packets transmission time in ALTX queue should not exceed the trap time.
                                     (The transmission time includes the response time required.)
                                     HW should stop ALTX queue when the TSF is trapped.
    CEASE_PSMP_TRAP0[10]         - (RW) To preserve the elasticity of the trap configuration, when this bit is enabled, the remaining packets transmission time in PSMP queue should not exceed the trap time.
                                     (The transmission time includes the response time required.)
                                     HW should stop PSMP queue when the TSF is trapped.
    CEASE_NAF_TRAP0[11]          - (RW) To preserve the elasticity of trap configuration, when this bit is enabled, the remaining packets transmission time in NAF queue should not exceed the trap time.
                                     (The transmission time includes the response time required.)
                                     HW should stop RWP queue when the TSF is trapped.
    CEASE_NBCN_TRAP0[12]         - (RW) To preserve the elasticity of trap configuration, when this bit is enabled, the remaining packets transmission time in NBCN queue should not exceed the trap time.
                                     (The transmission time includes the response time required.)
                                     HW should stop RWP queue when the TSF is trapped.
    RESERVED13[31..13]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_NBCN_TRAP0_ADDR           BN0_WF_LPON_TOP_TXTCR0_ADDR
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_NBCN_TRAP0_MASK           0x00001000                // CEASE_NBCN_TRAP0[12]
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_NBCN_TRAP0_SHFT           12
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_NAF_TRAP0_ADDR            BN0_WF_LPON_TOP_TXTCR0_ADDR
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_NAF_TRAP0_MASK            0x00000800                // CEASE_NAF_TRAP0[11]
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_NAF_TRAP0_SHFT            11
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_PSMP_TRAP0_ADDR           BN0_WF_LPON_TOP_TXTCR0_ADDR
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_PSMP_TRAP0_MASK           0x00000400                // CEASE_PSMP_TRAP0[10]
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_PSMP_TRAP0_SHFT           10
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_ALTX_TRAP0_ADDR           BN0_WF_LPON_TOP_TXTCR0_ADDR
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_ALTX_TRAP0_MASK           0x00000200                // CEASE_ALTX_TRAP0[9]
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_ALTX_TRAP0_SHFT           9
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_RWP_TRAP0_ADDR            BN0_WF_LPON_TOP_TXTCR0_ADDR
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_RWP_TRAP0_MASK            0x00000100                // CEASE_RWP_TRAP0[8]
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_RWP_TRAP0_SHFT            8
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_BMC_TRAP0_ADDR            BN0_WF_LPON_TOP_TXTCR0_ADDR
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_BMC_TRAP0_MASK            0x00000080                // CEASE_BMC_TRAP0[7]
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_BMC_TRAP0_SHFT            7
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_BCN_TRAP0_ADDR            BN0_WF_LPON_TOP_TXTCR0_ADDR
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_BCN_TRAP0_MASK            0x00000040                // CEASE_BCN_TRAP0[6]
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_BCN_TRAP0_SHFT            6
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_TX_TRAP0_ADDR             BN0_WF_LPON_TOP_TXTCR0_ADDR
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_TX_TRAP0_MASK             0x0000003C                // CEASE_TX_TRAP0[5..2]
#define BN0_WF_LPON_TOP_TXTCR0_CEASE_TX_TRAP0_SHFT             2
#define BN0_WF_LPON_TOP_TXTCR0_TRAP0_PERIOD_ONE_SHOT_ADDR      BN0_WF_LPON_TOP_TXTCR0_ADDR
#define BN0_WF_LPON_TOP_TXTCR0_TRAP0_PERIOD_ONE_SHOT_MASK      0x00000002                // TRAP0_PERIOD_ONE_SHOT[1]
#define BN0_WF_LPON_TOP_TXTCR0_TRAP0_PERIOD_ONE_SHOT_SHFT      1
#define BN0_WF_LPON_TOP_TXTCR0_TX_TRAP0_TIME_EN_ADDR           BN0_WF_LPON_TOP_TXTCR0_ADDR
#define BN0_WF_LPON_TOP_TXTCR0_TX_TRAP0_TIME_EN_MASK           0x00000001                // TX_TRAP0_TIME_EN[0]
#define BN0_WF_LPON_TOP_TXTCR0_TX_TRAP0_TIME_EN_SHFT           0

/* =====================================================================================

  ---TXTCR1 (0x820EB000 + 0x2dc)---

    TX_TRAP1_TIME_EN[0]          - (RW) Same as TX_TRAP0_TIME_EN
    TRAP1_PERIOD_ONE_SHOT[1]     - (RO) Same as TRAP0_PERIOD_ONE_SHOT
    CEASE_TX_TRAP1[5..2]         - (RW) Same as CEASE_TX_TRAP0
    CEASE_BCN_TRAP1[6]           - (RW) Same as CEASE_BCN_TRAP0
    CEASE_BMC_TRAP1[7]           - (RW) Same as CEASE_BMC_TRAP0
    CEASE_RWP_TRAP1[8]           - (RW) Same as CEASE_RWP_TRAP0
    CEASE_ALTX_TRAP1[9]          - (RW) Same as CEASE_ALTX_TRAP0
    CEASE_PSMP_TRAP1[10]         - (RW) Same as CEASE_PSMP_TRAP0
    CEASE_NAF_TRAP1[11]          - (RW) Same as CEASE_NAF_TRAP0
    CEASE_NBCN_TRAP1[12]         - (RW) Same as CEASE_NBCN_TRAP0
    RESERVED13[31..13]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_NBCN_TRAP1_ADDR           BN0_WF_LPON_TOP_TXTCR1_ADDR
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_NBCN_TRAP1_MASK           0x00001000                // CEASE_NBCN_TRAP1[12]
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_NBCN_TRAP1_SHFT           12
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_NAF_TRAP1_ADDR            BN0_WF_LPON_TOP_TXTCR1_ADDR
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_NAF_TRAP1_MASK            0x00000800                // CEASE_NAF_TRAP1[11]
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_NAF_TRAP1_SHFT            11
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_PSMP_TRAP1_ADDR           BN0_WF_LPON_TOP_TXTCR1_ADDR
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_PSMP_TRAP1_MASK           0x00000400                // CEASE_PSMP_TRAP1[10]
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_PSMP_TRAP1_SHFT           10
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_ALTX_TRAP1_ADDR           BN0_WF_LPON_TOP_TXTCR1_ADDR
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_ALTX_TRAP1_MASK           0x00000200                // CEASE_ALTX_TRAP1[9]
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_ALTX_TRAP1_SHFT           9
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_RWP_TRAP1_ADDR            BN0_WF_LPON_TOP_TXTCR1_ADDR
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_RWP_TRAP1_MASK            0x00000100                // CEASE_RWP_TRAP1[8]
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_RWP_TRAP1_SHFT            8
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_BMC_TRAP1_ADDR            BN0_WF_LPON_TOP_TXTCR1_ADDR
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_BMC_TRAP1_MASK            0x00000080                // CEASE_BMC_TRAP1[7]
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_BMC_TRAP1_SHFT            7
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_BCN_TRAP1_ADDR            BN0_WF_LPON_TOP_TXTCR1_ADDR
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_BCN_TRAP1_MASK            0x00000040                // CEASE_BCN_TRAP1[6]
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_BCN_TRAP1_SHFT            6
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_TX_TRAP1_ADDR             BN0_WF_LPON_TOP_TXTCR1_ADDR
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_TX_TRAP1_MASK             0x0000003C                // CEASE_TX_TRAP1[5..2]
#define BN0_WF_LPON_TOP_TXTCR1_CEASE_TX_TRAP1_SHFT             2
#define BN0_WF_LPON_TOP_TXTCR1_TRAP1_PERIOD_ONE_SHOT_ADDR      BN0_WF_LPON_TOP_TXTCR1_ADDR
#define BN0_WF_LPON_TOP_TXTCR1_TRAP1_PERIOD_ONE_SHOT_MASK      0x00000002                // TRAP1_PERIOD_ONE_SHOT[1]
#define BN0_WF_LPON_TOP_TXTCR1_TRAP1_PERIOD_ONE_SHOT_SHFT      1
#define BN0_WF_LPON_TOP_TXTCR1_TX_TRAP1_TIME_EN_ADDR           BN0_WF_LPON_TOP_TXTCR1_ADDR
#define BN0_WF_LPON_TOP_TXTCR1_TX_TRAP1_TIME_EN_MASK           0x00000001                // TX_TRAP1_TIME_EN[0]
#define BN0_WF_LPON_TOP_TXTCR1_TX_TRAP1_TIME_EN_SHFT           0

/* =====================================================================================

  ---TXTCR2 (0x820EB000 + 0x2e0)---

    TX_TRAP2_TIME_EN[0]          - (RW) Same as TX_TRAP0_TIME_EN
    TRAP2_PERIOD_ONE_SHOT[1]     - (RO) Same as TRAP0_PERIOD_ONE_SHOT
    CEASE_TX_TRAP2[5..2]         - (RW) Same as CEASE_TX_TRAP0
    CEASE_BCN_TRAP2[6]           - (RW) Same as CEASE_BCN_TRAP0
    CEASE_BMC_TRAP2[7]           - (RW) Same as CEASE_BMC_TRAP0
    CEASE_RWP_TRAP2[8]           - (RW) Same as CEASE_RWP_TRAP0
    CEASE_ALTX_TRAP2[9]          - (RW) Same as CEASE_ALTX_TRAP0
    CEASE_PSMP_TRAP2[10]         - (RW) Same as CEASE_PSMP_TRAP0
    CEASE_NAF_TRAP2[11]          - (RW) Same as CEASE_NAF_TRAP0
    CEASE_NBCN_TRAP2[12]         - (RW) Same as CEASE_NBCN_TRAP0
    RESERVED13[31..13]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_NBCN_TRAP2_ADDR           BN0_WF_LPON_TOP_TXTCR2_ADDR
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_NBCN_TRAP2_MASK           0x00001000                // CEASE_NBCN_TRAP2[12]
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_NBCN_TRAP2_SHFT           12
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_NAF_TRAP2_ADDR            BN0_WF_LPON_TOP_TXTCR2_ADDR
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_NAF_TRAP2_MASK            0x00000800                // CEASE_NAF_TRAP2[11]
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_NAF_TRAP2_SHFT            11
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_PSMP_TRAP2_ADDR           BN0_WF_LPON_TOP_TXTCR2_ADDR
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_PSMP_TRAP2_MASK           0x00000400                // CEASE_PSMP_TRAP2[10]
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_PSMP_TRAP2_SHFT           10
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_ALTX_TRAP2_ADDR           BN0_WF_LPON_TOP_TXTCR2_ADDR
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_ALTX_TRAP2_MASK           0x00000200                // CEASE_ALTX_TRAP2[9]
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_ALTX_TRAP2_SHFT           9
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_RWP_TRAP2_ADDR            BN0_WF_LPON_TOP_TXTCR2_ADDR
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_RWP_TRAP2_MASK            0x00000100                // CEASE_RWP_TRAP2[8]
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_RWP_TRAP2_SHFT            8
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_BMC_TRAP2_ADDR            BN0_WF_LPON_TOP_TXTCR2_ADDR
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_BMC_TRAP2_MASK            0x00000080                // CEASE_BMC_TRAP2[7]
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_BMC_TRAP2_SHFT            7
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_BCN_TRAP2_ADDR            BN0_WF_LPON_TOP_TXTCR2_ADDR
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_BCN_TRAP2_MASK            0x00000040                // CEASE_BCN_TRAP2[6]
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_BCN_TRAP2_SHFT            6
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_TX_TRAP2_ADDR             BN0_WF_LPON_TOP_TXTCR2_ADDR
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_TX_TRAP2_MASK             0x0000003C                // CEASE_TX_TRAP2[5..2]
#define BN0_WF_LPON_TOP_TXTCR2_CEASE_TX_TRAP2_SHFT             2
#define BN0_WF_LPON_TOP_TXTCR2_TRAP2_PERIOD_ONE_SHOT_ADDR      BN0_WF_LPON_TOP_TXTCR2_ADDR
#define BN0_WF_LPON_TOP_TXTCR2_TRAP2_PERIOD_ONE_SHOT_MASK      0x00000002                // TRAP2_PERIOD_ONE_SHOT[1]
#define BN0_WF_LPON_TOP_TXTCR2_TRAP2_PERIOD_ONE_SHOT_SHFT      1
#define BN0_WF_LPON_TOP_TXTCR2_TX_TRAP2_TIME_EN_ADDR           BN0_WF_LPON_TOP_TXTCR2_ADDR
#define BN0_WF_LPON_TOP_TXTCR2_TX_TRAP2_TIME_EN_MASK           0x00000001                // TX_TRAP2_TIME_EN[0]
#define BN0_WF_LPON_TOP_TXTCR2_TX_TRAP2_TIME_EN_SHFT           0

/* =====================================================================================

  ---TXTCR3 (0x820EB000 + 0x2e4)---

    TX_TRAP3_TIME_EN[0]          - (RW) Same as TX_TRAP0_TIME_EN
    TRAP3_PERIOD_ONE_SHOT[1]     - (RO) Same as TRAP0_PERIOD_ONE_SHOT
    CEASE_TX_TRAP3[5..2]         - (RW) Same as CEASE_TX_TRAP0
    CEASE_BCN_TRAP3[6]           - (RW) Same as CEASE_BCN_TRAP0
    CEASE_BMC_TRAP3[7]           - (RW) Same as CEASE_BMC_TRAP0
    CEASE_RWP_TRAP3[8]           - (RW) Same as CEASE_RWP_TRAP0
    CEASE_ALTX_TRAP3[9]          - (RW) Same as CEASE_ALTX_TRAP0
    CEASE_PSMP_TRAP3[10]         - (RW) Same as CEASE_PSMP_TRAP0
    CEASE_NAF_TRAP3[11]          - (RW) Same as CEASE_NAF_TRAP0
    CEASE_NBCN_TRAP3[12]         - (RW) Same as CEASE_NBCN_TRAP0
    RESERVED13[31..13]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_NBCN_TRAP3_ADDR           BN0_WF_LPON_TOP_TXTCR3_ADDR
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_NBCN_TRAP3_MASK           0x00001000                // CEASE_NBCN_TRAP3[12]
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_NBCN_TRAP3_SHFT           12
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_NAF_TRAP3_ADDR            BN0_WF_LPON_TOP_TXTCR3_ADDR
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_NAF_TRAP3_MASK            0x00000800                // CEASE_NAF_TRAP3[11]
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_NAF_TRAP3_SHFT            11
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_PSMP_TRAP3_ADDR           BN0_WF_LPON_TOP_TXTCR3_ADDR
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_PSMP_TRAP3_MASK           0x00000400                // CEASE_PSMP_TRAP3[10]
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_PSMP_TRAP3_SHFT           10
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_ALTX_TRAP3_ADDR           BN0_WF_LPON_TOP_TXTCR3_ADDR
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_ALTX_TRAP3_MASK           0x00000200                // CEASE_ALTX_TRAP3[9]
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_ALTX_TRAP3_SHFT           9
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_RWP_TRAP3_ADDR            BN0_WF_LPON_TOP_TXTCR3_ADDR
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_RWP_TRAP3_MASK            0x00000100                // CEASE_RWP_TRAP3[8]
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_RWP_TRAP3_SHFT            8
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_BMC_TRAP3_ADDR            BN0_WF_LPON_TOP_TXTCR3_ADDR
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_BMC_TRAP3_MASK            0x00000080                // CEASE_BMC_TRAP3[7]
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_BMC_TRAP3_SHFT            7
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_BCN_TRAP3_ADDR            BN0_WF_LPON_TOP_TXTCR3_ADDR
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_BCN_TRAP3_MASK            0x00000040                // CEASE_BCN_TRAP3[6]
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_BCN_TRAP3_SHFT            6
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_TX_TRAP3_ADDR             BN0_WF_LPON_TOP_TXTCR3_ADDR
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_TX_TRAP3_MASK             0x0000003C                // CEASE_TX_TRAP3[5..2]
#define BN0_WF_LPON_TOP_TXTCR3_CEASE_TX_TRAP3_SHFT             2
#define BN0_WF_LPON_TOP_TXTCR3_TRAP3_PERIOD_ONE_SHOT_ADDR      BN0_WF_LPON_TOP_TXTCR3_ADDR
#define BN0_WF_LPON_TOP_TXTCR3_TRAP3_PERIOD_ONE_SHOT_MASK      0x00000002                // TRAP3_PERIOD_ONE_SHOT[1]
#define BN0_WF_LPON_TOP_TXTCR3_TRAP3_PERIOD_ONE_SHOT_SHFT      1
#define BN0_WF_LPON_TOP_TXTCR3_TX_TRAP3_TIME_EN_ADDR           BN0_WF_LPON_TOP_TXTCR3_ADDR
#define BN0_WF_LPON_TOP_TXTCR3_TX_TRAP3_TIME_EN_MASK           0x00000001                // TX_TRAP3_TIME_EN[0]
#define BN0_WF_LPON_TOP_TXTCR3_TX_TRAP3_TIME_EN_SHFT           0

/* =====================================================================================

  ---MPTCR0 (0x820EB000 + 0x02e8)---

    TBTT0PERIODTIMER_EN[0]       - (W1S) Enables TBTT periodic time comparison for settings of BSS 0 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.TBTTPERIODTIMER_DIS to disable this function. Read returns the status of this bit setting.
    PRETBTT0_TRIG_EN[1]          - (W1S) Function for the setting of BSS 0
                                     This field is used to enable the TBTT timer capability to trigger MT7615 wakeup for every TTPCR.TBTTwakePeriod from sleep state to WLAN_on state. 
                                     This field is meaningful only when TBTTPERIODTIMER_EN is set to 1 and TTPCR.TBTTwakePeriod is larger than 0.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.PRETBTT_TRIG_DIS to disable this function. Read returns the status of this bit setting.
    PREDTIM0_TRIG_EN[2]          - (W1S) Function for the setting of BSS 0
                                     This field is used to enable the TBTT timer capability to trigger MT7615 wakeup for each TTPCR.DTIMwakePeriod from sleep state to WLAN_on state. 
                                     This field is meaningful only when TBTTPERIODTIMER_EN is set to 1 and TTPCR.DTIMwakePeriod is larger than 0.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.PREDTIM_TRIG_DIS to disable this function. Read returns the status of this bit setting.
    TBTT0TIMEUP_EN[3]            - (W1S) Function for the setting of BSS 0
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when TBTT timeup event occurs. Refer to WIS0R.TBTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.TBTTTIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    PRETBTT0TIMEUP_EN[4]         - (W1S) Function for the setting of BSS 0
                                     This field is used to control MT7615 for generating Pre-TBTT pulse when Pre-TBTT timeup event occurs. Refer to WIS0R.PRETBTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1. PRETBTTTIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    BCN_TIMEOUT0_EN[5]           - (W1S) Generates WIS0R.Bcn_Timeout when BSS 0 beacon frame is not received within the timeout period
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. The related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.bcn_timeout_count_limit setting. 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.BCN_TIMEOUT0_DIS to disable this function. Read returns the status of this bit setting.
    BMC_TIMEOUT0_EN[6]           - (W1S) Controls WIS0R.BMC_Timeout generation when receiving BSS 0 beacon with buffered broadcast indication or the received BMC frame from the same BSS will the moredata bit asserted and waiting for wanted BC/MC data packet timeout
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. The related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.BMC_timeout_count_limit setting.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.BMC_TIMEOUT0_DIS to disable this function. Read returns the status of this bit setting.
    PRETBTT0INT_EN[7]            - (W1S) Function for the setting of BSS 0
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when Pre-TBTT timeup event occurs. Refer to WIS0R.PRETBTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1. PRETBTTINT_DIS to disable this function. Read returns the status of this bit setting.
    TBTT1PERIODTIMER_EN[8]       - (W1S) Enables TBTT periodic time comparison for settings of BSS 1 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.TBTTPERIODTIMER_DIS to disable this function. Read returns the status of this bit setting.
    PRETBTT1_TRIG_EN[9]          - (W1S) Function for the setting of BSS 1
                                     This field is used to enable the TBTT timer capability to trigger MT7615 wakeup for every TTPCR.TBTTwakePeriod from sleep state to WLAN_on state. 
                                     This field is meaningful only when TBTTPERIODTIMER_EN is set to 1 and TTPCR.TBTTwakePeriod is larger than 0.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.PRETBTT_TRIG_DIS to disable this function. Read returns the status of this bit setting.
    PREDTIM1_TRIG_EN[10]         - (W1S) Function for the setting of BSS 1
                                     This field is used to enable the TBTT timer capability to trigger MT7615 wakeup for each (TTPCR.DTIMwakePeriod) from sleep state to WLAN_on state. 
                                     This field is meaningful only when TBTTPERIODTIMER_EN is set to 1 and TTPCR.DTIMwakePeriod is larger than 0.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.PREDTIM_TRIG_DIS to disable this function. Read returns the status of this bit setting.
    TBTT1TIMEUP_EN[11]           - (W1S) Function for the setting of BSS 1
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when TBTT timeup event occurs. Refer to WIS0R.TBTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.TBTTTIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    PRETBTT1TIMEUP_EN[12]        - (W1S) Function for the setting of BSS 1
                                     This field is used to control MT7615 for generating Pre-TBTT pulse when Pre-TBTT timeup event occurs. Refer to WIS0R.PRETBTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1. PRETBTTTIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    BCN_TIMEOUT1_EN[13]          - (W1S) Generates WIS0R.Bcn_Timeout when BSS 1 beacon frame is not received within the timeout period
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. The related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.bcn_timeout_count_limit setting. 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.BCN_TIMEOUT1_DIS to disable this function. Read returns the status of this bit setting.
    BMC_TIMEOUT1_EN[14]          - (W1S) Controls WIS0R.BMC_Timeout generation when receiving BSS 1 beacon with buffered broadcast indication or the received BMC frame from the same BSS will the moredata bit asserted and waiting for wanted BC/MC data packet timeout
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. The related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.BMC_timeout_count_limit setting.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.BMC_TIMEOUT1_DIS to disable this function. Read returns the status of this bit setting.
    PRETBTT1INT_EN[15]           - (W1S) Function for the setting of BSS 1
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when Pre-TBTT timeup event occurs. Refer to WIS0R.PRETBTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1. PRETBTTINT_DIS to disable this function. Read returns the status of this bit setting.
    T0TIMER_EN[16]               - (W1S) Enables T0 time comparison
                                     If enabled, the T0 start time will be updated according to its period when the local TSF value matches T0 timer. This is a TSF related timer. The related functions of T0 timer can be found in TTSR.timer_ctrl.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.T0TIMER _DIS to disable this function. Read returns the status of this bit setting.
    T1TIMER_EN[17]               - (W1S) Same as T0Timer_En
    T2TIMER_EN[18]               - (W1S) Same as T0Timer_En
    T3TIMER_EN[19]               - (W1S) Same as T0Timer_En
    T8TIMER_EN[20]               - (W1S) Controls timer T8 to start counting
                                     The T8 timer only has 16 bits. This is a free-run timer. The related functions of T8 timer can be found in TTSR.timer_ctrl.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.T8TIMER_EN_DIS to disable this function. Read returns the status of this bit setting.
    NDPA_TIMEOUT_EN[21]          - (W1S) Enables NDPA timeout function
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.NDPA_TIMEOUT_DIS to disable this function. Read returns the status of this bit setting.
    RESERVED22[26..22]           - (RO) Reserved bits
    BCN_PARSE_TIM0_EN[27]        - (W1S) This function is setting for BSSID 0.
                                     Enable MT7615 parsing TIM information of BSS 0 beacon frame for broadcast and unicast indication and DTIM count.
                                     If disabled, MT7615 will not parse TIM information of all BSS 0 beacons frame and all BSS 0 beacons frame will be received and wake up host.
                                     If enabled, MT7615 will parse BSS 0 beacon frame to get broadcast and unicast indication and update HW DTIM count.
    BCN_BMC0_EN[28]              - (W1S) This function is setting for BSSID 0.
                                     Enable MT7615 to check the broadcast indication in beacon frame TIM IE (from BSSID0) when MPTCR0.bcn_parse_tim0_en function is enabled and moredata bit in BC/MC frame from AP. Refer to SRS for more details.
                                     When this field is enabled, MT7615 will clear SPCR.BMC_SP0 when receiving a BC/MC from AP w/ moredata bit is 0 and set SPCR.BMC_SP when receiving a BC/MC from AP w/ moredata bit is 1 or receiving beacon w/ buffered broadcast indication (disregarding how RX filter is set). 
                                     When enabled, MT7615 will also drop the beacon frame from BSSID 0 w/ BMC indication bit asserted.
                                     In contrast, when disabled, the BSS 0 beacon frame w/ BMC indication bit asserted will be received and generate the interrupt of WISR0.RX_done to wake up MCUSYS.
    BCN_PARSE_TIM1_EN[29]        - (W1S) This function is setting for BSSID 1.
                                     Enable MT7615 parsing TIM information of BSS 1 beacon frame for broadcast and unicast indication and DTIM count.
                                     If disabled, MT7615 will not parse TIM information of all BSS 1 beacons frame and all BSS 1 beacons frame will be received and wake up host.
                                     If enabled, MT7615 will parse BSS 1 beacon frame to get broadcast and unicast indication and update HW DTIM count.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.BCN_PARSE_TIM1 _DIS to disable this function. Read returns the status of this bit setting.
    BCN_BMC1_EN[30]              - (W1S) This function is setting for BSSID 1.
                                     Enable MT7615 to check the broadcast indication in beacon frame TIM IE (from BSSID1) when MPTCR0.bcn_parse_tim1_en function is enabled and moredata bit in BC/MC frame from AP. Refer to SRS for more details.
                                     When this field is enabled, MT7615 will clear SPCR.BMC_SP1 when receiving a BC/MC from AP w/ moredata bit is 0 and set SPCR.BMC_SP1 when receiving a BC/MC from AP w/ moredata bit is 1 or receiving beacon w/ buffered broadcast indication (disregarding how RX filter is set). 
                                     When enabled, MT7615 will also drop the beacon frame from BSSID 1 w/ BMC indication bit asserted.
                                     In contrast, when disabled, the BSS 1 beacon frame w/ BMC indication bit asserted will be received and generate the interrupt of WISR0.RX_done to wake up MCUSYS. 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.BCN_BMC1_DIS to disable this function. Read returns the status of this bit setting.
    SP_END_CHK_EN[31]            - (W1S) Generates interrupt of WIS0R. SP_END by the combination end of the following SP
                                     This bit will also be helpful in MAC emulation automation.
                                     1) BMC_SP0
                                     2) BEACON_SP0
                                     3) BMC_SP1
                                     4) BEACON_SP1
                                     5) BMC_SP2
                                     6) BEACON_SP2
                                     7) BMC_SP3
                                     8) BEACON_SP3
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.SP_END_CHK_DIS to disable this function.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MPTCR0_SP_END_CHK_EN_ADDR              BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_SP_END_CHK_EN_MASK              0x80000000                // SP_END_CHK_EN[31]
#define BN0_WF_LPON_TOP_MPTCR0_SP_END_CHK_EN_SHFT              31
#define BN0_WF_LPON_TOP_MPTCR0_BCN_BMC1_EN_ADDR                BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_BCN_BMC1_EN_MASK                0x40000000                // BCN_BMC1_EN[30]
#define BN0_WF_LPON_TOP_MPTCR0_BCN_BMC1_EN_SHFT                30
#define BN0_WF_LPON_TOP_MPTCR0_BCN_PARSE_TIM1_EN_ADDR          BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_BCN_PARSE_TIM1_EN_MASK          0x20000000                // BCN_PARSE_TIM1_EN[29]
#define BN0_WF_LPON_TOP_MPTCR0_BCN_PARSE_TIM1_EN_SHFT          29
#define BN0_WF_LPON_TOP_MPTCR0_BCN_BMC0_EN_ADDR                BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_BCN_BMC0_EN_MASK                0x10000000                // BCN_BMC0_EN[28]
#define BN0_WF_LPON_TOP_MPTCR0_BCN_BMC0_EN_SHFT                28
#define BN0_WF_LPON_TOP_MPTCR0_BCN_PARSE_TIM0_EN_ADDR          BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_BCN_PARSE_TIM0_EN_MASK          0x08000000                // BCN_PARSE_TIM0_EN[27]
#define BN0_WF_LPON_TOP_MPTCR0_BCN_PARSE_TIM0_EN_SHFT          27
#define BN0_WF_LPON_TOP_MPTCR0_NDPA_TIMEOUT_EN_ADDR            BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_NDPA_TIMEOUT_EN_MASK            0x00200000                // NDPA_TIMEOUT_EN[21]
#define BN0_WF_LPON_TOP_MPTCR0_NDPA_TIMEOUT_EN_SHFT            21
#define BN0_WF_LPON_TOP_MPTCR0_T8TIMER_EN_ADDR                 BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_T8TIMER_EN_MASK                 0x00100000                // T8TIMER_EN[20]
#define BN0_WF_LPON_TOP_MPTCR0_T8TIMER_EN_SHFT                 20
#define BN0_WF_LPON_TOP_MPTCR0_T3TIMER_EN_ADDR                 BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_T3TIMER_EN_MASK                 0x00080000                // T3TIMER_EN[19]
#define BN0_WF_LPON_TOP_MPTCR0_T3TIMER_EN_SHFT                 19
#define BN0_WF_LPON_TOP_MPTCR0_T2TIMER_EN_ADDR                 BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_T2TIMER_EN_MASK                 0x00040000                // T2TIMER_EN[18]
#define BN0_WF_LPON_TOP_MPTCR0_T2TIMER_EN_SHFT                 18
#define BN0_WF_LPON_TOP_MPTCR0_T1TIMER_EN_ADDR                 BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_T1TIMER_EN_MASK                 0x00020000                // T1TIMER_EN[17]
#define BN0_WF_LPON_TOP_MPTCR0_T1TIMER_EN_SHFT                 17
#define BN0_WF_LPON_TOP_MPTCR0_T0TIMER_EN_ADDR                 BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_T0TIMER_EN_MASK                 0x00010000                // T0TIMER_EN[16]
#define BN0_WF_LPON_TOP_MPTCR0_T0TIMER_EN_SHFT                 16
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT1INT_EN_ADDR             BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT1INT_EN_MASK             0x00008000                // PRETBTT1INT_EN[15]
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT1INT_EN_SHFT             15
#define BN0_WF_LPON_TOP_MPTCR0_BMC_TIMEOUT1_EN_ADDR            BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_BMC_TIMEOUT1_EN_MASK            0x00004000                // BMC_TIMEOUT1_EN[14]
#define BN0_WF_LPON_TOP_MPTCR0_BMC_TIMEOUT1_EN_SHFT            14
#define BN0_WF_LPON_TOP_MPTCR0_BCN_TIMEOUT1_EN_ADDR            BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_BCN_TIMEOUT1_EN_MASK            0x00002000                // BCN_TIMEOUT1_EN[13]
#define BN0_WF_LPON_TOP_MPTCR0_BCN_TIMEOUT1_EN_SHFT            13
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT1TIMEUP_EN_ADDR          BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT1TIMEUP_EN_MASK          0x00001000                // PRETBTT1TIMEUP_EN[12]
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT1TIMEUP_EN_SHFT          12
#define BN0_WF_LPON_TOP_MPTCR0_TBTT1TIMEUP_EN_ADDR             BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_TBTT1TIMEUP_EN_MASK             0x00000800                // TBTT1TIMEUP_EN[11]
#define BN0_WF_LPON_TOP_MPTCR0_TBTT1TIMEUP_EN_SHFT             11
#define BN0_WF_LPON_TOP_MPTCR0_PREDTIM1_TRIG_EN_ADDR           BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_PREDTIM1_TRIG_EN_MASK           0x00000400                // PREDTIM1_TRIG_EN[10]
#define BN0_WF_LPON_TOP_MPTCR0_PREDTIM1_TRIG_EN_SHFT           10
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT1_TRIG_EN_ADDR           BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT1_TRIG_EN_MASK           0x00000200                // PRETBTT1_TRIG_EN[9]
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT1_TRIG_EN_SHFT           9
#define BN0_WF_LPON_TOP_MPTCR0_TBTT1PERIODTIMER_EN_ADDR        BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_TBTT1PERIODTIMER_EN_MASK        0x00000100                // TBTT1PERIODTIMER_EN[8]
#define BN0_WF_LPON_TOP_MPTCR0_TBTT1PERIODTIMER_EN_SHFT        8
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT0INT_EN_ADDR             BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT0INT_EN_MASK             0x00000080                // PRETBTT0INT_EN[7]
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT0INT_EN_SHFT             7
#define BN0_WF_LPON_TOP_MPTCR0_BMC_TIMEOUT0_EN_ADDR            BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_BMC_TIMEOUT0_EN_MASK            0x00000040                // BMC_TIMEOUT0_EN[6]
#define BN0_WF_LPON_TOP_MPTCR0_BMC_TIMEOUT0_EN_SHFT            6
#define BN0_WF_LPON_TOP_MPTCR0_BCN_TIMEOUT0_EN_ADDR            BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_BCN_TIMEOUT0_EN_MASK            0x00000020                // BCN_TIMEOUT0_EN[5]
#define BN0_WF_LPON_TOP_MPTCR0_BCN_TIMEOUT0_EN_SHFT            5
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT0TIMEUP_EN_ADDR          BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT0TIMEUP_EN_MASK          0x00000010                // PRETBTT0TIMEUP_EN[4]
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT0TIMEUP_EN_SHFT          4
#define BN0_WF_LPON_TOP_MPTCR0_TBTT0TIMEUP_EN_ADDR             BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_TBTT0TIMEUP_EN_MASK             0x00000008                // TBTT0TIMEUP_EN[3]
#define BN0_WF_LPON_TOP_MPTCR0_TBTT0TIMEUP_EN_SHFT             3
#define BN0_WF_LPON_TOP_MPTCR0_PREDTIM0_TRIG_EN_ADDR           BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_PREDTIM0_TRIG_EN_MASK           0x00000004                // PREDTIM0_TRIG_EN[2]
#define BN0_WF_LPON_TOP_MPTCR0_PREDTIM0_TRIG_EN_SHFT           2
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT0_TRIG_EN_ADDR           BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT0_TRIG_EN_MASK           0x00000002                // PRETBTT0_TRIG_EN[1]
#define BN0_WF_LPON_TOP_MPTCR0_PRETBTT0_TRIG_EN_SHFT           1
#define BN0_WF_LPON_TOP_MPTCR0_TBTT0PERIODTIMER_EN_ADDR        BN0_WF_LPON_TOP_MPTCR0_ADDR
#define BN0_WF_LPON_TOP_MPTCR0_TBTT0PERIODTIMER_EN_MASK        0x00000001                // TBTT0PERIODTIMER_EN[0]
#define BN0_WF_LPON_TOP_MPTCR0_TBTT0PERIODTIMER_EN_SHFT        0

/* =====================================================================================

  ---MPTCR2 (0x820EB000 + 0x2ec)---

    TBTT2PERIODTIMER_EN[0]       - (W1S) Enables TBTT periodic time comparison for settings of BSS 2
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP3.TBTTPERIODTIMER_DIS to disable this function. Read returns the status of this bit setting.
    PRETBTT2_TRIG_EN[1]          - (W1S) Function for the setting of BSS 2
                                     This field is used to enable the TBTT timer capability to trigger MT7615 wakeup for every TTPCR.TBTTwakePeriod from sleep state to WLAN_on state. 
                                     This field is meaningful only when TBTTPERIODTIMER_EN is set to 1 and TTPCR.TBTTwakePeriod is larger than 0.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP3.PRETBTT_TRIG_DIS to disable this function. Read returns the status of this bit setting.
    PREDTIM2_TRIG_EN[2]          - (W1S) Function for the setting of BSS 2
                                     This field is used to enable the TBTT timer capability to trigger MT7615 wakeup for each TTPCR.DTIMwakePeriod from sleep state to WLAN_on state. 
                                     This field is meaningful only when TBTTPERIODTIMER_EN is set to 1 and TTPCR.DTIMwakePeriod is larger than 0.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.PREDTIM_TRIG_DIS to disable this function. Read returns the status of this bit setting.
    TBTT2TIMEUP_EN[3]            - (W1S) Function for the setting of BSS 2
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when TBTT timeup event occurs. Refer to WISR3.TBTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP3.TBTTTIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    PRETBTT2TIMEUP_EN[4]         - (W1S) Function for the setting of BSS 2
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when Pre-TBTT timeup event occurs. Refer to WISR3.PRETBTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP3. PRETBTTTIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    BCN_TIMEOUT2_EN[5]           - (W1S) Generates WISR3.Bcn_Timeout when BSS 2 beacon frame is not received within the timeout period
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. The related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.bcn_timeout_count_limit setting. 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP3.BCN_TIMEOUT2_DIS to disable this function. Read returns the status of this bit setting.
    BMC_TIMEOUT2_EN[6]           - (W1S) Controls WISR3.BMC_Timeout generation when receiving BSS 2 beacon with buffered broadcast indication or the received BMC frame from the same BSS will the moredata bit asserted and waiting for wanted BC/MC data packet timeout
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. The related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.BMC_timeout_count_limit setting.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP1.BMC_TIMEOUT2_DIS to disable this function. Read returns the status of this bit setting.
    PRETBTT2_INT_EN[7]           - (W1S) Function for the setting of BSS 2
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when PRETBTT timeup event occurs.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP3.PRETBTT2_INT_DIS to disable this function. Read returns the status of this bit setting.
    TBTT3PERIODTIMER_EN[8]       - (W1S) Enables TBTT periodic time comparison for settings of BSS 3
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP3.TBTTPERIODTIMER_DIS to disable this function. Read returns the status of this bit setting.
    PRETBTT3_TRIG_EN[9]          - (W1S) Function for the setting of BSS 3
                                     This field is used to enable the TBTT timer capability to trigger MT7615 wakeup for every TTPCR.TBTTwakePeriod from sleep state to WLAN_on state. 
                                     This field is meaningful only when TBTTPERIODTIMER_EN is set to 1 and TTPCR.TBTTwakePeriod is larger than 0.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP3.PRETBTT_TRIG_DIS to disable this function. Read returns the status of this bit setting.
    PREDTIM3_TRIG_EN[10]         - (W1S) Function for the setting of BSS 3
                                     This field is used to enable the TBTT timer capability to trigger MT7615 wakeup for each TTPCR.DTIMwakePeriod from sleep state to WLAN_on state. 
                                     This field is meaningful only when TBTTPERIODTIMER_EN is set to 1 and TTPCR.DTIMwakePeriod is larger than 0.
                                     Writing 0 has no meaning, write 1 to enable. Write 1 to MPTCP1.PREDTIM_TRIG_DIS to disable this function. Read returns the status of this bit setting.
    TBTT3TIMEUP_EN[11]           - (W1S) Function for the setting of BSS 3
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when TBTT timeup event occurs. Refer to WISR3.TBTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP3.TBTTTIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    PRETBTT3TIMEUP_EN[12]        - (W1S) Function for the setting of BSS 3
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when Pre-TBTT timeup event occurs. Refer to WISR3.PRETBTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP3. PRETBTTTIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    BCN_TIMEOUT3_EN[13]          - (W1S) Generates WISR3.Bcn_Timeout when BSS 3 beacon frame is not received within the timeout period
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. The related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.bcn_timeout_count_limit setting. 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP3.BCN_TIMEOUT3_DIS to disable this function. Read returns the status of this bit setting.
    BMC_TIMEOUT3_EN[14]          - (W1S) Controls WISR3.BMC_Timeout generation when receiving BSS 3 beacon with buffered broadcast indication or the received BMC frame from the same BSS will the moredata bit asserted and waiting for wanted BC/MC data packet timeout
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. And the related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.BMC_timeout_count_limit setting.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP3.BMC_TIMEOUT3_DIS to disable this function. Read returns the status of this bit setting.
    PRETBTT3_INT_EN[15]          - (W1S) Function for the setting of BSS 3
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when PRETBTT timeup event occurs.
                                     Writing 0 has no meaning, and write 1 to Enable.
                                     Write 1 to MPTCP3.PRETBTT3_INT_DIS to disable this function
                                     Read returns the status of this bit setting.
    RESERVED16[26..16]           - (RO) Reserved bits
    BCN_PARSE_TIM2_EN[27]        - (W1S) This function is setting for BSSID 2.
                                     Enable MT7615 parsing TIM information of BSS 2 beacon frame for broadcast and unicast indication and DTIM count.
                                     If disabled, MT7615 will not parse TIM information of all BSS 2 beacons frame and all BSS 2 beacons frame will be received and wake up host.
                                     If enabled, MT7615 will parse BSS 2 beacon frame to get broadcast and unicast indication and update HW DTIM count
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP3.BCN_PARSE_TIM2 _DIS to disable this function. Read returns the status of this bit setting.
    BCN_BMC2_EN[28]              - (W1S) This function is setting for BSSID 2.
                                     Enable MT7615 to check the broadcast indication in beacon frame TIM IE (from BSSID2) when MPTCR3.bcn_parse_tim2_en function is enabled and moredata bit in BC/MC frame from AP. Refer to SRS for more details.
                                     When this field is enabled, MT7615 will clear SPCR.BMC_SP2 when receiving a BC/MC from AP w/ moredata bit is 0 and set SPCR.BMC_SP when receiving a BC/MC from AP w/ moredata bit is 1 or receiving beacon w/ buffered broadcast indication (disregarding how RX filter is set). 
                                     When enabled, MT7615 will also drop the beacon frame from BSSID 2 w/ BMC indication bit asserted.
                                     In contrast, when disabled, the BSS 2 beacon frame w/ BMC indication bit asserted will be received and generate the interrupt of WISR0.RX_done to wake up MCUSYS. 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP3.BCN_BMC2_DIS to disable this function. Read returns the status of this bit setting.
    BCN_PARSE_TIM3_EN[29]        - (W1S) This function is setting for BSSID 3.
                                     Enable MT7615 parsing TIM information of BSS 3 beacon frame for broadcast and unicast indication and DTIM count.
                                     
                                     If disabled, MT7615 will not parse TIM information of all BSS 3 beacons frame and all BSS 3 beacons frame will be received and wake up host
                                     If enabled, MT7615 will parse BSS 3 beacon frame to get broadcast and unicast indication and update HW DTIM count
                                     
                                     Writing 0 has no meaning; write 1 to enable. 
                                     Write 1 to MPTCP3.BCN_PARSE_TIM3 _DIS to disable this function
                                     Read returns the status of this bit setting.
    BCN_BMC3_EN[30]              - (W1S) This function is setting for BSSID 3.
                                     Enable MT7615 to check the broadcast indication in beacon frame TIM IE (from BSSID3) when MPTCR2.bcn_parse_tim3_en function is enabled and moredata bit in BC/MC frame from AP. Refer to SRS for more details.
                                     When this field is enabled, MT7615 will clear SPCR.BMC_SP3 when receiving a BC/MC from AP w/ moredata bit is 0 and set SPCR.BMC_SP3 when receiving a BC/MC from AP w/ moredata bit is 1 or receiving beacon w/ buffered broadcast indication (disregarding how RX filter is set). 
                                     When enabled, MT7615 will also drop the beacon frame from BSSID 3 w/ BMC indication bit asserted.
                                     In contrast, when disabled, the BSS 3 beacon frame w/ BMC indication bit asserted will be received and generate the interrupt of WISR0.RX_done to wake up MCUSYS. 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP3.BCN_BMC3_DIS to disable this function. Read returns the status of this bit setting.
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MPTCR2_BCN_BMC3_EN_ADDR                BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_BCN_BMC3_EN_MASK                0x40000000                // BCN_BMC3_EN[30]
#define BN0_WF_LPON_TOP_MPTCR2_BCN_BMC3_EN_SHFT                30
#define BN0_WF_LPON_TOP_MPTCR2_BCN_PARSE_TIM3_EN_ADDR          BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_BCN_PARSE_TIM3_EN_MASK          0x20000000                // BCN_PARSE_TIM3_EN[29]
#define BN0_WF_LPON_TOP_MPTCR2_BCN_PARSE_TIM3_EN_SHFT          29
#define BN0_WF_LPON_TOP_MPTCR2_BCN_BMC2_EN_ADDR                BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_BCN_BMC2_EN_MASK                0x10000000                // BCN_BMC2_EN[28]
#define BN0_WF_LPON_TOP_MPTCR2_BCN_BMC2_EN_SHFT                28
#define BN0_WF_LPON_TOP_MPTCR2_BCN_PARSE_TIM2_EN_ADDR          BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_BCN_PARSE_TIM2_EN_MASK          0x08000000                // BCN_PARSE_TIM2_EN[27]
#define BN0_WF_LPON_TOP_MPTCR2_BCN_PARSE_TIM2_EN_SHFT          27
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT3_INT_EN_ADDR            BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT3_INT_EN_MASK            0x00008000                // PRETBTT3_INT_EN[15]
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT3_INT_EN_SHFT            15
#define BN0_WF_LPON_TOP_MPTCR2_BMC_TIMEOUT3_EN_ADDR            BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_BMC_TIMEOUT3_EN_MASK            0x00004000                // BMC_TIMEOUT3_EN[14]
#define BN0_WF_LPON_TOP_MPTCR2_BMC_TIMEOUT3_EN_SHFT            14
#define BN0_WF_LPON_TOP_MPTCR2_BCN_TIMEOUT3_EN_ADDR            BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_BCN_TIMEOUT3_EN_MASK            0x00002000                // BCN_TIMEOUT3_EN[13]
#define BN0_WF_LPON_TOP_MPTCR2_BCN_TIMEOUT3_EN_SHFT            13
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT3TIMEUP_EN_ADDR          BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT3TIMEUP_EN_MASK          0x00001000                // PRETBTT3TIMEUP_EN[12]
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT3TIMEUP_EN_SHFT          12
#define BN0_WF_LPON_TOP_MPTCR2_TBTT3TIMEUP_EN_ADDR             BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_TBTT3TIMEUP_EN_MASK             0x00000800                // TBTT3TIMEUP_EN[11]
#define BN0_WF_LPON_TOP_MPTCR2_TBTT3TIMEUP_EN_SHFT             11
#define BN0_WF_LPON_TOP_MPTCR2_PREDTIM3_TRIG_EN_ADDR           BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_PREDTIM3_TRIG_EN_MASK           0x00000400                // PREDTIM3_TRIG_EN[10]
#define BN0_WF_LPON_TOP_MPTCR2_PREDTIM3_TRIG_EN_SHFT           10
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT3_TRIG_EN_ADDR           BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT3_TRIG_EN_MASK           0x00000200                // PRETBTT3_TRIG_EN[9]
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT3_TRIG_EN_SHFT           9
#define BN0_WF_LPON_TOP_MPTCR2_TBTT3PERIODTIMER_EN_ADDR        BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_TBTT3PERIODTIMER_EN_MASK        0x00000100                // TBTT3PERIODTIMER_EN[8]
#define BN0_WF_LPON_TOP_MPTCR2_TBTT3PERIODTIMER_EN_SHFT        8
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT2_INT_EN_ADDR            BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT2_INT_EN_MASK            0x00000080                // PRETBTT2_INT_EN[7]
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT2_INT_EN_SHFT            7
#define BN0_WF_LPON_TOP_MPTCR2_BMC_TIMEOUT2_EN_ADDR            BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_BMC_TIMEOUT2_EN_MASK            0x00000040                // BMC_TIMEOUT2_EN[6]
#define BN0_WF_LPON_TOP_MPTCR2_BMC_TIMEOUT2_EN_SHFT            6
#define BN0_WF_LPON_TOP_MPTCR2_BCN_TIMEOUT2_EN_ADDR            BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_BCN_TIMEOUT2_EN_MASK            0x00000020                // BCN_TIMEOUT2_EN[5]
#define BN0_WF_LPON_TOP_MPTCR2_BCN_TIMEOUT2_EN_SHFT            5
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT2TIMEUP_EN_ADDR          BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT2TIMEUP_EN_MASK          0x00000010                // PRETBTT2TIMEUP_EN[4]
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT2TIMEUP_EN_SHFT          4
#define BN0_WF_LPON_TOP_MPTCR2_TBTT2TIMEUP_EN_ADDR             BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_TBTT2TIMEUP_EN_MASK             0x00000008                // TBTT2TIMEUP_EN[3]
#define BN0_WF_LPON_TOP_MPTCR2_TBTT2TIMEUP_EN_SHFT             3
#define BN0_WF_LPON_TOP_MPTCR2_PREDTIM2_TRIG_EN_ADDR           BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_PREDTIM2_TRIG_EN_MASK           0x00000004                // PREDTIM2_TRIG_EN[2]
#define BN0_WF_LPON_TOP_MPTCR2_PREDTIM2_TRIG_EN_SHFT           2
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT2_TRIG_EN_ADDR           BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT2_TRIG_EN_MASK           0x00000002                // PRETBTT2_TRIG_EN[1]
#define BN0_WF_LPON_TOP_MPTCR2_PRETBTT2_TRIG_EN_SHFT           1
#define BN0_WF_LPON_TOP_MPTCR2_TBTT2PERIODTIMER_EN_ADDR        BN0_WF_LPON_TOP_MPTCR2_ADDR
#define BN0_WF_LPON_TOP_MPTCR2_TBTT2PERIODTIMER_EN_MASK        0x00000001                // TBTT2PERIODTIMER_EN[0]
#define BN0_WF_LPON_TOP_MPTCR2_TBTT2PERIODTIMER_EN_SHFT        0

/* =====================================================================================

  ---MPTCR4 (0x820EB000 + 0x2f0)---

    TTTT0PERIODTIMER_EN[0]       - (W1S) Enables TTTT periodic time comparison for settings of BSS 0
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5.TTTTPERIODTIMER_DIS to disable this function. Read returns the status of this bit setting.
    PRETTTT0_TRIG_EN[1]          - (W1S) Function for the setting of BSS 0
                                     This field is used to enable the TTTT timer capability to trigger MT7615 wakeup for every TTPCR.TTTTwakePeriod from sleep state to WLAN_on state. 
                                     This field is meaningful only when TTTTPERIODTIMER_EN is set to 1 and TTPCR.TTTTwakePeriod is larger than 0.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5.PRETTTT_TRIG_DIS to disable this function. Read returns the status of this bit setting.
    RESERVED2[2]                 - (RO) Reserved bits
    TTTT0TIMEUP_EN[3]            - (W1S) Function for the setting of BSS0
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when TTTT timeup event occurs. Refer to WISR3.TTTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5.TTTTTIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    PRETTTT0TIMEUP_EN[4]         - (W1S) Function for the setting of BSS 0
                                     This field is used to control MT7615 for generating pre-TTTT pulse (it will transit LP state to ON state) when Pre-TTTT timeup event occurs. Refer to WISR3.PRETTTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5 PRETTTTTIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    TIM_TIMEOUT0_EN[5]           - (W1S) Generates WISR3.TIM_Timeout when BSS 0 TIM frame is not received within the timeout period
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. The related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.bcn_timeout_count_limit setting. 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5.TIM_TIMEOUT0_DIS to disable this function. Read returns the status of this bit setting.
    TIM_BMC_TIMEOUT0_EN[6]       - (W1S) Controls WISR3.TIM_BMC_Timeout generation when receiving BSS 0 beacon with buffered broadcast indication or the received BMC frame from the same BSS will the moredata bit asserted and waiting for wanted BC/MC data packet timeout
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. The related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.BMC_timeout_count_limit setting.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5.BMC_TIMEOUT0_DIS to disable this function. Read returns the status of this bit setting.
    PRETTTT0INT_EN[7]            - (W1S) Function for the setting of BSS 0
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when Pre-TTTT timeup event occurs. Refer to WISR3.PRETTTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5 PRETTTTINT_DIS to disable this function. Read returns the status of this bit setting.
    TTTT1PERIODTIMER_EN[8]       - (W1S) Enables TTTT periodic time comparison for settings of BSS 1
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5.TTTTPERIODTIMER_DIS to disable this function. Read returns the status of this bit setting.
    PRETTTT1_TRIG_EN[9]          - (W1S) Function for the setting of BSS 3
                                     This field is used to enable the TTTT timer capability to trigger MT7615 wakeup for every TTPCR.TTTTwakePeriod from sleep state to WLAN_on state. 
                                     This field is meaningful only when TTTTPERIODTIMER_EN is set to 1 and TTPCR.TTTTwakePeriod is larger than 0.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5.PRETTTT_TRIG_DIS to disable this function. Read returns the status of this bit setting.
    RESERVED10[10]               - (RO) Reserved bits
    TTTT1TIMEUP_EN[11]           - (W1S) Function for the setting of BSS 1
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when TTTT timeup event occurs. Refer to WISR3.TTTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5.TTTTTIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    PRETTTT1TIMEUP_EN[12]        - (W1S) Function for the setting of BSS 1
                                     This field is used to control MT7615 for generating pre-TTTT pulse (it will transit LP state to ON state) when Pre-TTTT timeup event occurs. Refer to WISR3.PRETTTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5. PRETTTTTIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    TIM_TIMEOUT1_EN[13]          - (W1S) Generates WISR3.TIM_Timeout when BSS 1 TIM frame is not received within the timeout period
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. The related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.bcn_timeout_count_limit setting. 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5.TIM_TIMEOUT1_DIS to disable this function. Read returns the status of this bit setting.
    TIM_BMC_TIMEOUT1_EN[14]      - (W1S) Controls WISR3.TIM_BMC_Timeout generation when receiving BSS 1 beacon with buffered broadcast indication or the received BMC frame from the same BSS will the moredata bit asserted and waiting for wanted BC/MC data packet timeout
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. The related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.BMC_timeout_count_limit setting.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5.TIM_BMC_TIMEOUT1_DIS to disable this function. Read returns the status of this bit setting.
    PRETTTT1INT_EN[15]           - (W1S) Function for the setting of BSS 1
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when Pre-TTTT timeup event occurs. Refer to WISR3.PRETTTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5. PRETTTTINT_DIS to disable this function. Read returns the status of this bit setting.
    RESERVED16[26..16]           - (RO) Reserved bits
    TIM_PARSE_TIM0_EN[27]        - (W1S) This function is setting for BSSID 0.
                                     Enable MT7615 parsing TIM information of BSS 0 beacon frame for broadcast and unicast indication and DTIM count.
                                     If disabled, MT7615 will not parse TIM information of all BSS 0 TIMs frame and all BSS 0 TIMs frame will be received and wake up host.
                                     If enabled, MT7615 will parse BSS 0 TIM frame to get broadcast and unicast indication and update HW DTIM count.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5.TIM_PARSE_TIM0 _DIS to disable this function. Read returns the status of this bit setting.
    TIM_BMC0_EN[28]              - (W1S) This function is setting for BSSID 0.
                                     Enable MT7615 to check the broadcast indication in beacon frame TIM IE (from BSSID0) when MPTCR0.bcn_parse_tim0_en function is enabled and moredata bit in BC/MC frame from AP. Refer to SRS for more details.
                                     When this field is enabled, MT7615 will clear SPCR.BMC_SP0 when receiving a BC/MC from AP w/ moredata bit is 0 and set SPCR.BMC_SP when receiving a BC/MC from AP w/ moredata bit is 1 or receiving beacon w/ buffered broadcast indication (disregarding how RX filter is set). 
                                     When enabled, MT7615 will also drop the beacon frame from BSSID0 w/ BMC indication bit asserted.
                                     In contrast, when disabled, the BSS 0 TIM frame w/ BMC indication bit asserted will be received and generate the interrupt of WISR0.RX_done to wake up MCUSYS. 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5.TIM_BMC0_DIS to disable this function. Read returns the status of this bit setting.
    TIM_PARSE_TIM1_EN[29]        - (W1S) This function is setting for BSSID 1.
                                     Enable MT7615 parsing TIM information of BSS 1 beacon frame for broadcast and unicast indication and DTIM count.
                                     If disabled, MT7615 will not parse TIM information of all BSS 1TIMs frame and all BSS 1 TIMs frame will be received and wake up host.
                                     If enabled, MT7615 will parse BSS 1 TIM frame to get broadcast and unicast indication and update HW DTIM count.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5.TIM_PARSE_TIM1 _DIS to disable this function. Read returns the status of this bit setting.
    TIM_BMC1_EN[30]              - (W1S) This function is setting for BSSID 1.
                                     Enable MT7615 to check the broadcast indication in beacon frame TIM IE (from BSSID1) when MPTCR0.bcn_parse_tim1_en function is enabled and moredata bit in BC/MC frame from AP. Refer to SRS for more details.
                                     When this field is enabled, MT7615 will clear SPCR.BMC_SP1 when receiving a BC/MC from AP w/ moredata bit is 0 and set SPCR.BMC_SP1 when receiving a BC/MC from AP w/ moredata bit is 1 or receiving beacon w/ buffered broadcast indication (disregarding how RX filter is set). 
                                     When enabled, MT7615 will also drop the beacon frame from BSSID 1 w/ BMC indication bit asserted.
                                     In contrast, when disabled, the BSS 1 beacon frame w/ BMC indication bit asserted will be received and generate the interrupt of WISR0.RX_done to wake up MCUSYS. 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR5.TIM_BMC1_DIS to disable this function. Read returns the status of this bit setting.
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MPTCR4_TIM_BMC1_EN_ADDR                BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_TIM_BMC1_EN_MASK                0x40000000                // TIM_BMC1_EN[30]
#define BN0_WF_LPON_TOP_MPTCR4_TIM_BMC1_EN_SHFT                30
#define BN0_WF_LPON_TOP_MPTCR4_TIM_PARSE_TIM1_EN_ADDR          BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_TIM_PARSE_TIM1_EN_MASK          0x20000000                // TIM_PARSE_TIM1_EN[29]
#define BN0_WF_LPON_TOP_MPTCR4_TIM_PARSE_TIM1_EN_SHFT          29
#define BN0_WF_LPON_TOP_MPTCR4_TIM_BMC0_EN_ADDR                BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_TIM_BMC0_EN_MASK                0x10000000                // TIM_BMC0_EN[28]
#define BN0_WF_LPON_TOP_MPTCR4_TIM_BMC0_EN_SHFT                28
#define BN0_WF_LPON_TOP_MPTCR4_TIM_PARSE_TIM0_EN_ADDR          BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_TIM_PARSE_TIM0_EN_MASK          0x08000000                // TIM_PARSE_TIM0_EN[27]
#define BN0_WF_LPON_TOP_MPTCR4_TIM_PARSE_TIM0_EN_SHFT          27
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT1INT_EN_ADDR             BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT1INT_EN_MASK             0x00008000                // PRETTTT1INT_EN[15]
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT1INT_EN_SHFT             15
#define BN0_WF_LPON_TOP_MPTCR4_TIM_BMC_TIMEOUT1_EN_ADDR        BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_TIM_BMC_TIMEOUT1_EN_MASK        0x00004000                // TIM_BMC_TIMEOUT1_EN[14]
#define BN0_WF_LPON_TOP_MPTCR4_TIM_BMC_TIMEOUT1_EN_SHFT        14
#define BN0_WF_LPON_TOP_MPTCR4_TIM_TIMEOUT1_EN_ADDR            BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_TIM_TIMEOUT1_EN_MASK            0x00002000                // TIM_TIMEOUT1_EN[13]
#define BN0_WF_LPON_TOP_MPTCR4_TIM_TIMEOUT1_EN_SHFT            13
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT1TIMEUP_EN_ADDR          BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT1TIMEUP_EN_MASK          0x00001000                // PRETTTT1TIMEUP_EN[12]
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT1TIMEUP_EN_SHFT          12
#define BN0_WF_LPON_TOP_MPTCR4_TTTT1TIMEUP_EN_ADDR             BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_TTTT1TIMEUP_EN_MASK             0x00000800                // TTTT1TIMEUP_EN[11]
#define BN0_WF_LPON_TOP_MPTCR4_TTTT1TIMEUP_EN_SHFT             11
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT1_TRIG_EN_ADDR           BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT1_TRIG_EN_MASK           0x00000200                // PRETTTT1_TRIG_EN[9]
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT1_TRIG_EN_SHFT           9
#define BN0_WF_LPON_TOP_MPTCR4_TTTT1PERIODTIMER_EN_ADDR        BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_TTTT1PERIODTIMER_EN_MASK        0x00000100                // TTTT1PERIODTIMER_EN[8]
#define BN0_WF_LPON_TOP_MPTCR4_TTTT1PERIODTIMER_EN_SHFT        8
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT0INT_EN_ADDR             BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT0INT_EN_MASK             0x00000080                // PRETTTT0INT_EN[7]
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT0INT_EN_SHFT             7
#define BN0_WF_LPON_TOP_MPTCR4_TIM_BMC_TIMEOUT0_EN_ADDR        BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_TIM_BMC_TIMEOUT0_EN_MASK        0x00000040                // TIM_BMC_TIMEOUT0_EN[6]
#define BN0_WF_LPON_TOP_MPTCR4_TIM_BMC_TIMEOUT0_EN_SHFT        6
#define BN0_WF_LPON_TOP_MPTCR4_TIM_TIMEOUT0_EN_ADDR            BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_TIM_TIMEOUT0_EN_MASK            0x00000020                // TIM_TIMEOUT0_EN[5]
#define BN0_WF_LPON_TOP_MPTCR4_TIM_TIMEOUT0_EN_SHFT            5
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT0TIMEUP_EN_ADDR          BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT0TIMEUP_EN_MASK          0x00000010                // PRETTTT0TIMEUP_EN[4]
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT0TIMEUP_EN_SHFT          4
#define BN0_WF_LPON_TOP_MPTCR4_TTTT0TIMEUP_EN_ADDR             BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_TTTT0TIMEUP_EN_MASK             0x00000008                // TTTT0TIMEUP_EN[3]
#define BN0_WF_LPON_TOP_MPTCR4_TTTT0TIMEUP_EN_SHFT             3
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT0_TRIG_EN_ADDR           BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT0_TRIG_EN_MASK           0x00000002                // PRETTTT0_TRIG_EN[1]
#define BN0_WF_LPON_TOP_MPTCR4_PRETTTT0_TRIG_EN_SHFT           1
#define BN0_WF_LPON_TOP_MPTCR4_TTTT0PERIODTIMER_EN_ADDR        BN0_WF_LPON_TOP_MPTCR4_ADDR
#define BN0_WF_LPON_TOP_MPTCR4_TTTT0PERIODTIMER_EN_MASK        0x00000001                // TTTT0PERIODTIMER_EN[0]
#define BN0_WF_LPON_TOP_MPTCR4_TTTT0PERIODTIMER_EN_SHFT        0

/* =====================================================================================

  ---MPTCR6 (0x820EB000 + 0x2f4)---

    TTTT2PERIODTIMER_EN[0]       - (W1S) Enables TTTT periodic time comparison for settings of BSS 2 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7.TTTT2PERIODTIMER_DIS to disable this function. Read returns the status of this bit setting.
    PRETTTT2_TRIG_EN[1]          - (W1S) Function for the setting of BSS 2
                                     This field is used to enable the TTTT timer capability to trigger MT7615 wakeup for every TTPCR.TTTTwakePeriod from sleep state to WLAN_on state. 
                                     This field is meaningful only when TTTTPERIODTIMER_EN is set to 1 and TTPCR.TTTTwakePeriod is larger than 0.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7.PRETTTT2_TRIG_DIS to disable this function. Read returns the status of this bit setting.
    RESERVED2[2]                 - (RO) Reserved bits
    TTTT2TIMEUP_EN[3]            - (W1S) Function for the setting of BSS2
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when TTTT timeup event occurs. Refer to WISR3.TTTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7.TTTT2TIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    PRETTTT2TIMEUP_EN[4]         - (W1S) Function for the setting of BSS 2
                                     This field is used to control MT7615 for generating pre-TTTT pulse (it will transit LP state to ON state) when Pre-TTTT timeup event occurs. Refer to WISR3.PRETTTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7 PRETTTT2TIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    TIM_TIMEOUT2_EN[5]           - (W1S) Generates WISR3.TIM_Timeout when BSS 2 TIM frame is not received within the timeout period
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. The related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.bcn_timeout_count_limit setting. 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7.TIM_TIMEOUT2_DIS to disable this function. Read returns the status of this bit setting.
    TIM_BMC_TIMEOUT2_EN[6]       - (W1S) Controls WISR3.TIM_BMC_Timeout generation when receiving BSS 2 beacon with buffered broadcast indication or the received BMC frame from the same BSS will the moredata bit asserted and waiting for wanted BC/MC data packet timeout
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. The related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.BMC_timeout_count_limit setting.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7.BMC_TIMEOUT2_DIS to disable this function. Read returns the status of this bit setting.
    PRETTTT2INT_EN[7]            - (W1S) Function for the setting of BSS 2
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when Pre-TTTT timeup event occurs. Refer to WISR3.PRETTTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7 PRETTTT2INT_DIS to disable this function. Read returns the status of this bit setting.
    TTTT3PERIODTIMER_EN[8]       - (W1S) Enables TTTT periodic time comparison for settings of BSS 3
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7.TTTT3PERIODTIMER_DIS to disable this function. Read returns the status of this bit setting.
    PRETTTT3_TRIG_EN[9]          - (W1S) Function for the setting of BSS 3.
                                     This field is used to enable the TTTT timer capability to trigger MT7615 wakeup for every TTPCR.TTTTwakePeriod from sleep state to WLAN_on state. This field is meaningful only when TTTTPERIODTIMER_EN is set to 1 and TTPCR.TTTTwakePeriod is larger than 0.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7.PRETTTT3_TRIG_DIS to disable this function. Read returns the status of this bit setting.
    RESERVED10[10]               - (RO) Reserved bits
    TTTT3TIMEUP_EN[11]           - (W1S) Function for the setting of BSS 3
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when TTTT timeup event occurs. Refer to WISR3.TTTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7.TTTT3TIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    PRETTTT3TIMEUP_EN[12]        - (W1S) Function for the setting of BSS 3
                                     This field is used to control MT7615 for generating pre-TTTT pulse (it will transit LP state to ON state) when Pre-TTTT timeup event occurs. Refer to WISR3.PRETTTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7. PRETTTT3TIMEUP_DIS to disable this function. Read returns the status of this bit setting.
    TIM_TIMEOUT3_EN[13]          - (W1S) Generates WISR3.TIM_Timeout when BSS 3 TIM frame is not received within the timeout period
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. The related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.bcn_timeout_count_limit setting. 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7.TIM_TIMEOUT3_DIS to disable this function. Read returns the status of this bit setting.
    TIM_BMC_TIMEOUT3_EN[14]      - (W1S) Controls WISR3.TIM_BMC_Timeout generation when receiving BSS 3 beacon with buffered broadcast indication or the received BMC frame from the same BSS will the moredata bit asserted and waiting for wanted BC/MC data packet timeout
                                     If this bit is not asserted, MT7615 will not return to sleep due to this timeout event. The related interrupt timeout status will be asserted until this timeout event occurs according to TCLCR.BMC_timeout_count_limit setting.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7.TIM_BMC_TIMEOUT3_DIS to disable this function. Read returns the status of this bit setting.
    PRETTTT3INT_EN[15]           - (W1S) It is the function for the setting of BSS 3.
                                     This field is used to control MT7615 for generating interrupt (it will transit LP state to ON state) when Pre-TTTT timeup event occurs. Refer to WISR3.PRETTTT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7. PRETTTT3INT_DIS to disable this function. Read returns the status of this bit setting.
    RESERVED16[26..16]           - (RO) Reserved bits
    TIM_PARSE_TIM2_EN[27]        - (W1S) This function is setting for BSSID 2.
                                     Enable MT7615 parsing TIM information of BSS 2 beacon frame for broadcast and unicast indication and DTIM count.
                                     If disabled, MT7615 will not parse TIM information of all BSS 2 TIMs frame and all BSS 2 TIMs frame will be received and wake up host.
                                     If enabled, MT7615 will parse BSS 2 TIM frame to get broadcast and unicast indication and update HW DTIM count.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7.TIM_PARSE_TIM2 _DIS to disable this function. Read returns the status of this bit setting.
    TIM_BMC2_EN[28]              - (W1S) This function is setting for BSSID 2.
                                     Enable MT7615 to check the broadcast indication in beacon frame TIM IE (from BSSID2) when MPTCR2.bcn_parse_tim2_en function is enabled and moredata bit in BC/MC frame from AP. Refer to SRS for more details.
                                     When this field is enabled, MT7615 will clear SPCR.BMC_SP2 when receiving a BC/MC from AP w/ moredata bit is 0 and set SPCR.BMC_SP2 when receiving a BC/MC from AP w/ moredata bit is 1 or receiving beacon w/ buffered broadcast indication (disregarding how RX filter is set). 
                                     When enabled, MT7615 will drop the beacon frame from BSSID2 w/ BMC indication bit asserted.
                                     In contrast, when disabled, the BSS 2 TIM frame w/ BMC indication bit asserted will be received and generate the interrupt of WISR0.RX_done to wake up MCUSYS. 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7.TIM_BMC2_DIS to disable this function. Read returns the status of this bit setting.
    TIM_PARSE_TIM3_EN[29]        - (W1S) This function is setting for BSSID 3.
                                     Enable MT7615 parsing TIM information of BSS 3 beacon frame for broadcast and unicast indication and DTIM count.
                                     If disabled, MT7615 will not parse TIM information of all BSS 3TIMs frame and all BSS 3 TIMs frame will be received and wake up host
                                     If enabled, MT7615 will parse BSS 3 TIM frame to get broadcast and unicast indication and update HW DTIM count
                                     
                                     Writing 0 has no meaning; write 1 to enable. 
                                     Write 1 to MPTCR7.TIM_PARSE_TIM1 _DIS to disable this function
                                     Read returns the status of this bit setting.
    TIM_BMC3_EN[30]              - (W1S) This function is setting for BSSID 3.
                                     Enable MT7615 to check the broadcast indication in beacon frame TIM IE (from BSSID3) when MPTCR2.bcn_parse_tim3_en function is enabled and moredata bit in BC/MC frame from AP. Refer to SRS for more details.
                                     When this field is enabled, MT7615 will clear SPCR.BMC_SP3 when receiving a BC/MC from AP w/ moredata bit is 0 and set SPCR.BMC_SP3 when receiving a BC/MC from AP w/ moredata bit is 1 or receiving beacon w/ buffered broadcast indication (disregarding how RX filter is set). 
                                     When enabled, MT7615 will also drop the beacon frame from BSSID 3 w/ BMC indication bit asserted.
                                     In contrast, when disabled, the BSS 3 beacon frame w/ BMC indication bit asserted will be received and generate the interrupt of WISR0.RX_done to wake up MCUSYS. 
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCR7.TIM_BMC1_DIS to disable this function. Read returns the status of this bit setting.
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MPTCR6_TIM_BMC3_EN_ADDR                BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_TIM_BMC3_EN_MASK                0x40000000                // TIM_BMC3_EN[30]
#define BN0_WF_LPON_TOP_MPTCR6_TIM_BMC3_EN_SHFT                30
#define BN0_WF_LPON_TOP_MPTCR6_TIM_PARSE_TIM3_EN_ADDR          BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_TIM_PARSE_TIM3_EN_MASK          0x20000000                // TIM_PARSE_TIM3_EN[29]
#define BN0_WF_LPON_TOP_MPTCR6_TIM_PARSE_TIM3_EN_SHFT          29
#define BN0_WF_LPON_TOP_MPTCR6_TIM_BMC2_EN_ADDR                BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_TIM_BMC2_EN_MASK                0x10000000                // TIM_BMC2_EN[28]
#define BN0_WF_LPON_TOP_MPTCR6_TIM_BMC2_EN_SHFT                28
#define BN0_WF_LPON_TOP_MPTCR6_TIM_PARSE_TIM2_EN_ADDR          BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_TIM_PARSE_TIM2_EN_MASK          0x08000000                // TIM_PARSE_TIM2_EN[27]
#define BN0_WF_LPON_TOP_MPTCR6_TIM_PARSE_TIM2_EN_SHFT          27
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT3INT_EN_ADDR             BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT3INT_EN_MASK             0x00008000                // PRETTTT3INT_EN[15]
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT3INT_EN_SHFT             15
#define BN0_WF_LPON_TOP_MPTCR6_TIM_BMC_TIMEOUT3_EN_ADDR        BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_TIM_BMC_TIMEOUT3_EN_MASK        0x00004000                // TIM_BMC_TIMEOUT3_EN[14]
#define BN0_WF_LPON_TOP_MPTCR6_TIM_BMC_TIMEOUT3_EN_SHFT        14
#define BN0_WF_LPON_TOP_MPTCR6_TIM_TIMEOUT3_EN_ADDR            BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_TIM_TIMEOUT3_EN_MASK            0x00002000                // TIM_TIMEOUT3_EN[13]
#define BN0_WF_LPON_TOP_MPTCR6_TIM_TIMEOUT3_EN_SHFT            13
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT3TIMEUP_EN_ADDR          BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT3TIMEUP_EN_MASK          0x00001000                // PRETTTT3TIMEUP_EN[12]
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT3TIMEUP_EN_SHFT          12
#define BN0_WF_LPON_TOP_MPTCR6_TTTT3TIMEUP_EN_ADDR             BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_TTTT3TIMEUP_EN_MASK             0x00000800                // TTTT3TIMEUP_EN[11]
#define BN0_WF_LPON_TOP_MPTCR6_TTTT3TIMEUP_EN_SHFT             11
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT3_TRIG_EN_ADDR           BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT3_TRIG_EN_MASK           0x00000200                // PRETTTT3_TRIG_EN[9]
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT3_TRIG_EN_SHFT           9
#define BN0_WF_LPON_TOP_MPTCR6_TTTT3PERIODTIMER_EN_ADDR        BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_TTTT3PERIODTIMER_EN_MASK        0x00000100                // TTTT3PERIODTIMER_EN[8]
#define BN0_WF_LPON_TOP_MPTCR6_TTTT3PERIODTIMER_EN_SHFT        8
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT2INT_EN_ADDR             BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT2INT_EN_MASK             0x00000080                // PRETTTT2INT_EN[7]
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT2INT_EN_SHFT             7
#define BN0_WF_LPON_TOP_MPTCR6_TIM_BMC_TIMEOUT2_EN_ADDR        BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_TIM_BMC_TIMEOUT2_EN_MASK        0x00000040                // TIM_BMC_TIMEOUT2_EN[6]
#define BN0_WF_LPON_TOP_MPTCR6_TIM_BMC_TIMEOUT2_EN_SHFT        6
#define BN0_WF_LPON_TOP_MPTCR6_TIM_TIMEOUT2_EN_ADDR            BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_TIM_TIMEOUT2_EN_MASK            0x00000020                // TIM_TIMEOUT2_EN[5]
#define BN0_WF_LPON_TOP_MPTCR6_TIM_TIMEOUT2_EN_SHFT            5
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT2TIMEUP_EN_ADDR          BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT2TIMEUP_EN_MASK          0x00000010                // PRETTTT2TIMEUP_EN[4]
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT2TIMEUP_EN_SHFT          4
#define BN0_WF_LPON_TOP_MPTCR6_TTTT2TIMEUP_EN_ADDR             BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_TTTT2TIMEUP_EN_MASK             0x00000008                // TTTT2TIMEUP_EN[3]
#define BN0_WF_LPON_TOP_MPTCR6_TTTT2TIMEUP_EN_SHFT             3
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT2_TRIG_EN_ADDR           BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT2_TRIG_EN_MASK           0x00000002                // PRETTTT2_TRIG_EN[1]
#define BN0_WF_LPON_TOP_MPTCR6_PRETTTT2_TRIG_EN_SHFT           1
#define BN0_WF_LPON_TOP_MPTCR6_TTTT2PERIODTIMER_EN_ADDR        BN0_WF_LPON_TOP_MPTCR6_ADDR
#define BN0_WF_LPON_TOP_MPTCR6_TTTT2PERIODTIMER_EN_MASK        0x00000001                // TTTT2PERIODTIMER_EN[0]
#define BN0_WF_LPON_TOP_MPTCR6_TTTT2PERIODTIMER_EN_SHFT        0

/* =====================================================================================

  ---MPTCR8 (0x820EB000 + 0x2f8)---

    TWT0TIMER_EN[0]              - (W1S) Enables TWT0 time comparison
                                     If enabled, the TWT0 start time will be updated according to its period when the local TSF value matches TWT0 timer. This is a TSF related timer. The related functions of TWT0 timer can be found in TWT0CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.TWT0TIMER _DIS to disable this function. Read returns the status of this bit setting.
    TWT0TIMER_INT_EN[1]          - (W1S) This field is used to control TWT timer for generating interrupt (it will transit LP state to ON state) when TWT timeup event occurs. Refer to WIS8R.TWT0_INT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9. TWT0TIMER_INT_DIS to disable this function. Read returns the status of this bit setting.
    RESERVED2[7..2]              - (RO) Reserved bits
    TWT1TIMER_EN[8]              - (W1S) Enables TWT1 time comparison
                                     If enabled, the TWT1 start time will be updated according to its period when the local TSF value matches TWT1 timer. This is a TSF related timer. The related functions of TWT1 timer can be found in TWT1CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.TWT1TIMER _DIS to disable this function. Read returns the status of this bit setting.
    TWT1TIMER_INT_EN[9]          - (W1S) This field is used to control TWT timer for generating interrupt (it will transit LP state to ON state) when TWT timeup event occurs. Refer to WIS8R.TWT1_INT.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9. TWT1TIMER_INT_DIS to disable this function. Read returns the status of this bit setting.
    RESERVED10[15..10]           - (RO) Reserved bits
    MU_EDCA0_TIMER_EN[16]        - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.
    MU_EDCA1_TIMER_EN[17]        - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.
    MU_EDCA2_TIMER_EN[18]        - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.
    MU_EDCA3_TIMER_EN[19]        - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.
    MU_EDCA4_TIMER_EN[20]        - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.
    MU_EDCA5_TIMER_EN[21]        - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.
    MU_EDCA6_TIMER_EN[22]        - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.
    MU_EDCA7_TIMER_EN[23]        - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.
    MU_EDCA8_TIMER_EN[24]        - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.
    MU_EDCA9_TIMER_EN[25]        - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.
    MU_EDCA10_TIMER_EN[26]       - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.
    MU_EDCA11_TIMER_EN[27]       - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.
    MU_EDCA12_TIMER_EN[28]       - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.
    MU_EDCA13_TIMER_EN[29]       - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.
    MU_EDCA14_TIMER_EN[30]       - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.
    MU_EDCA15_TIMER_EN[31]       - (W1S) Enables MU_EDCA time comparison
                                     If enabled, the MU_EDCA end time will be updated by AGG set according to the local TSF value plus EDCA timer value to MU EDCA target timer. This is a TSF related timer. The related functions of MU EDCA timer can be found in MU_EDCA_CR.
                                     Writing 0 has no meaning; write 1 to enable. Write 1 to MPTCP9.MU_EDCATIMER _DIS to disable this function. Read returns the status of this bit setting.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA15_TIMER_EN_ADDR         BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA15_TIMER_EN_MASK         0x80000000                // MU_EDCA15_TIMER_EN[31]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA15_TIMER_EN_SHFT         31
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA14_TIMER_EN_ADDR         BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA14_TIMER_EN_MASK         0x40000000                // MU_EDCA14_TIMER_EN[30]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA14_TIMER_EN_SHFT         30
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA13_TIMER_EN_ADDR         BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA13_TIMER_EN_MASK         0x20000000                // MU_EDCA13_TIMER_EN[29]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA13_TIMER_EN_SHFT         29
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA12_TIMER_EN_ADDR         BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA12_TIMER_EN_MASK         0x10000000                // MU_EDCA12_TIMER_EN[28]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA12_TIMER_EN_SHFT         28
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA11_TIMER_EN_ADDR         BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA11_TIMER_EN_MASK         0x08000000                // MU_EDCA11_TIMER_EN[27]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA11_TIMER_EN_SHFT         27
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA10_TIMER_EN_ADDR         BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA10_TIMER_EN_MASK         0x04000000                // MU_EDCA10_TIMER_EN[26]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA10_TIMER_EN_SHFT         26
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA9_TIMER_EN_ADDR          BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA9_TIMER_EN_MASK          0x02000000                // MU_EDCA9_TIMER_EN[25]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA9_TIMER_EN_SHFT          25
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA8_TIMER_EN_ADDR          BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA8_TIMER_EN_MASK          0x01000000                // MU_EDCA8_TIMER_EN[24]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA8_TIMER_EN_SHFT          24
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA7_TIMER_EN_ADDR          BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA7_TIMER_EN_MASK          0x00800000                // MU_EDCA7_TIMER_EN[23]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA7_TIMER_EN_SHFT          23
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA6_TIMER_EN_ADDR          BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA6_TIMER_EN_MASK          0x00400000                // MU_EDCA6_TIMER_EN[22]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA6_TIMER_EN_SHFT          22
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA5_TIMER_EN_ADDR          BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA5_TIMER_EN_MASK          0x00200000                // MU_EDCA5_TIMER_EN[21]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA5_TIMER_EN_SHFT          21
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA4_TIMER_EN_ADDR          BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA4_TIMER_EN_MASK          0x00100000                // MU_EDCA4_TIMER_EN[20]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA4_TIMER_EN_SHFT          20
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA3_TIMER_EN_ADDR          BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA3_TIMER_EN_MASK          0x00080000                // MU_EDCA3_TIMER_EN[19]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA3_TIMER_EN_SHFT          19
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA2_TIMER_EN_ADDR          BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA2_TIMER_EN_MASK          0x00040000                // MU_EDCA2_TIMER_EN[18]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA2_TIMER_EN_SHFT          18
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA1_TIMER_EN_ADDR          BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA1_TIMER_EN_MASK          0x00020000                // MU_EDCA1_TIMER_EN[17]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA1_TIMER_EN_SHFT          17
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA0_TIMER_EN_ADDR          BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA0_TIMER_EN_MASK          0x00010000                // MU_EDCA0_TIMER_EN[16]
#define BN0_WF_LPON_TOP_MPTCR8_MU_EDCA0_TIMER_EN_SHFT          16
#define BN0_WF_LPON_TOP_MPTCR8_TWT1TIMER_INT_EN_ADDR           BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_TWT1TIMER_INT_EN_MASK           0x00000200                // TWT1TIMER_INT_EN[9]
#define BN0_WF_LPON_TOP_MPTCR8_TWT1TIMER_INT_EN_SHFT           9
#define BN0_WF_LPON_TOP_MPTCR8_TWT1TIMER_EN_ADDR               BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_TWT1TIMER_EN_MASK               0x00000100                // TWT1TIMER_EN[8]
#define BN0_WF_LPON_TOP_MPTCR8_TWT1TIMER_EN_SHFT               8
#define BN0_WF_LPON_TOP_MPTCR8_TWT0TIMER_INT_EN_ADDR           BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_TWT0TIMER_INT_EN_MASK           0x00000002                // TWT0TIMER_INT_EN[1]
#define BN0_WF_LPON_TOP_MPTCR8_TWT0TIMER_INT_EN_SHFT           1
#define BN0_WF_LPON_TOP_MPTCR8_TWT0TIMER_EN_ADDR               BN0_WF_LPON_TOP_MPTCR8_ADDR
#define BN0_WF_LPON_TOP_MPTCR8_TWT0TIMER_EN_MASK               0x00000001                // TWT0TIMER_EN[0]
#define BN0_WF_LPON_TOP_MPTCR8_TWT0TIMER_EN_SHFT               0

/* =====================================================================================

  ---DUMMY1 (0x820EB000 + 0x2fc)---

    DUMMY1[31..0]                - (RW) DUMMY register 1

 =====================================================================================*/
#define BN0_WF_LPON_TOP_DUMMY1_DUMMY1_ADDR                     BN0_WF_LPON_TOP_DUMMY1_ADDR
#define BN0_WF_LPON_TOP_DUMMY1_DUMMY1_MASK                     0xFFFFFFFF                // DUMMY1[31..0]
#define BN0_WF_LPON_TOP_DUMMY1_DUMMY1_SHFT                     0

/* =====================================================================================

  ---MPTCR1 (0x820EB000 + 0x300)---

    TBTT0PERIODTIMER_DIS[0]      - (WO) See MPTCR0. TBTT0PERIODTIMER_EN definition for how to disable corresponding function.
    PRETBTT0_TRIG_DIS[1]         - (WO) See MPTCR0.PRETBTT0_TRIG_EN definition for how to disable corresponding function
    PREDTIM0_TRIG_DIS[2]         - (WO) See MPTCR0.PREDTIM0_TRIG_EN definition for how to disable corresponding function
    TBTT0TIMEUP_DIS[3]           - (WO) See MPTCR0.TBTT0TIMEUP_EN definition for how to disable corresponding function.
    PRETBTT0TIMEUP_DIS[4]        - (WO) See MPTCR0.PRETBTT0TIMEUP_EN definition for how to disable corresponding function.
    BCN_TIMEOUT0_DIS[5]          - (WO) See MPTCR0. BCN_TIMEOUT0_EN definition for how to disable corresponding function.
    BMC_TIMEOUT0_DIS[6]          - (WO) See MPTCR0. BMC_TIMEOUT0_EN definition for how to disable corresponding function.
    PRETBTT0INT_DIS[7]           - (WO) See MPTCR0. PRETBTT0INT_EN definition for how to disable corresponding function.
    TBTT1PERIODTIMER_DIS[8]      - (WO) See MPTCR0. TBTT1PERIODTIMER_EN definition for how to disable corresponding function.
    PRETBTT1_TRIG_DIS[9]         - (WO) See MPTCR0.PRETBTT1_TRIG_EN definition for how to disable corresponding function.
    PREDTIM1_TRIG_DIS[10]        - (WO) See MPTCR0.PREDTIM1_TRIG_EN definition for how to disable corresponding function.
    TBTT1TIMEUP_DIS[11]          - (WO) See MPTCR0.TBTT1TIMEUP_EN definition for how to disable corresponding function.
    PRETBTT1TIMEUP_DIS[12]       - (WO) See MPTCR0.PRETBTT1TIMEUP_EN definition for how to disable corresponding function.
    BCN_TIMEOUT1_DIS[13]         - (WO) See MPTCR0. BCN_TIMEOUT1_EN definition for how to disable corresponding function.
    BMC_TIMEOUT1_DIS[14]         - (WO) See MPTCR0. BMC_TIMEOUT1_EN definition for how to disable corresponding function.
    PRETBTT1INT_DIS[15]          - (WO) See MPTCR0. PRETBTT1INT_EN definition for how to disable corresponding function.
    T0TIMER_DIS[16]              - (WO) See MPTCR0. T0TIMER_EN definition for how to disable corresponding function.
    T1TIMER_DIS[17]              - (WO) See MPTCR0. T1TIMER_EN definition for how to disable corresponding function.
    T2TIMER_DIS[18]              - (WO) See MPTCR0. T2TIMER_EN definition for how to disable corresponding function.
    T3TIMER_DIS[19]              - (WO) See MPTCR0. T3TIMER_EN definition for how to disable corresponding function.
    T8TIMER_DIS[20]              - (WO) See MPTCR0. T8TIMER_EN definition for how to disable corresponding function.
    NDPA_TIMEOUT_DIS[21]         - (WO) See MPTCR0. NDPA_TIMEOUT_EN definition for how to disable corresponding function.
    RESERVED22[26..22]           - (RO) Reserved bits
    BCN_PARSE_TIM0_DIS[27]       - (WO) See MPTCR0.BCN_PARSE_TIM0_EN definition for how to disable corresponding function.
    BCN_BMC0_DIS[28]             - (WO) See MPTCR0. BCN_BMC0_EN definition for how to disable corresponding function.
    BCN_PARSE_TIM1_DIS[29]       - (WO) See MPTCR0.BCN_PARSE_TIM1_EN definition for how to disable corresponding function.
    BCN_BMC1_DIS[30]             - (WO) See MPTCR0. BCN_BMC1_EN definition for how to disable corresponding function.
    SP_DISD_CHK_DIS[31]          - (WO) See MPTCR0. SP_END_CHK _EN definition for how to disable corresponding function.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MPTCR1_SP_DISD_CHK_DIS_ADDR            BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_SP_DISD_CHK_DIS_MASK            0x80000000                // SP_DISD_CHK_DIS[31]
#define BN0_WF_LPON_TOP_MPTCR1_SP_DISD_CHK_DIS_SHFT            31
#define BN0_WF_LPON_TOP_MPTCR1_BCN_BMC1_DIS_ADDR               BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_BCN_BMC1_DIS_MASK               0x40000000                // BCN_BMC1_DIS[30]
#define BN0_WF_LPON_TOP_MPTCR1_BCN_BMC1_DIS_SHFT               30
#define BN0_WF_LPON_TOP_MPTCR1_BCN_PARSE_TIM1_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_BCN_PARSE_TIM1_DIS_MASK         0x20000000                // BCN_PARSE_TIM1_DIS[29]
#define BN0_WF_LPON_TOP_MPTCR1_BCN_PARSE_TIM1_DIS_SHFT         29
#define BN0_WF_LPON_TOP_MPTCR1_BCN_BMC0_DIS_ADDR               BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_BCN_BMC0_DIS_MASK               0x10000000                // BCN_BMC0_DIS[28]
#define BN0_WF_LPON_TOP_MPTCR1_BCN_BMC0_DIS_SHFT               28
#define BN0_WF_LPON_TOP_MPTCR1_BCN_PARSE_TIM0_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_BCN_PARSE_TIM0_DIS_MASK         0x08000000                // BCN_PARSE_TIM0_DIS[27]
#define BN0_WF_LPON_TOP_MPTCR1_BCN_PARSE_TIM0_DIS_SHFT         27
#define BN0_WF_LPON_TOP_MPTCR1_NDPA_TIMEOUT_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_NDPA_TIMEOUT_DIS_MASK           0x00200000                // NDPA_TIMEOUT_DIS[21]
#define BN0_WF_LPON_TOP_MPTCR1_NDPA_TIMEOUT_DIS_SHFT           21
#define BN0_WF_LPON_TOP_MPTCR1_T8TIMER_DIS_ADDR                BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_T8TIMER_DIS_MASK                0x00100000                // T8TIMER_DIS[20]
#define BN0_WF_LPON_TOP_MPTCR1_T8TIMER_DIS_SHFT                20
#define BN0_WF_LPON_TOP_MPTCR1_T3TIMER_DIS_ADDR                BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_T3TIMER_DIS_MASK                0x00080000                // T3TIMER_DIS[19]
#define BN0_WF_LPON_TOP_MPTCR1_T3TIMER_DIS_SHFT                19
#define BN0_WF_LPON_TOP_MPTCR1_T2TIMER_DIS_ADDR                BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_T2TIMER_DIS_MASK                0x00040000                // T2TIMER_DIS[18]
#define BN0_WF_LPON_TOP_MPTCR1_T2TIMER_DIS_SHFT                18
#define BN0_WF_LPON_TOP_MPTCR1_T1TIMER_DIS_ADDR                BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_T1TIMER_DIS_MASK                0x00020000                // T1TIMER_DIS[17]
#define BN0_WF_LPON_TOP_MPTCR1_T1TIMER_DIS_SHFT                17
#define BN0_WF_LPON_TOP_MPTCR1_T0TIMER_DIS_ADDR                BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_T0TIMER_DIS_MASK                0x00010000                // T0TIMER_DIS[16]
#define BN0_WF_LPON_TOP_MPTCR1_T0TIMER_DIS_SHFT                16
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT1INT_DIS_ADDR            BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT1INT_DIS_MASK            0x00008000                // PRETBTT1INT_DIS[15]
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT1INT_DIS_SHFT            15
#define BN0_WF_LPON_TOP_MPTCR1_BMC_TIMEOUT1_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_BMC_TIMEOUT1_DIS_MASK           0x00004000                // BMC_TIMEOUT1_DIS[14]
#define BN0_WF_LPON_TOP_MPTCR1_BMC_TIMEOUT1_DIS_SHFT           14
#define BN0_WF_LPON_TOP_MPTCR1_BCN_TIMEOUT1_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_BCN_TIMEOUT1_DIS_MASK           0x00002000                // BCN_TIMEOUT1_DIS[13]
#define BN0_WF_LPON_TOP_MPTCR1_BCN_TIMEOUT1_DIS_SHFT           13
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT1TIMEUP_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT1TIMEUP_DIS_MASK         0x00001000                // PRETBTT1TIMEUP_DIS[12]
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT1TIMEUP_DIS_SHFT         12
#define BN0_WF_LPON_TOP_MPTCR1_TBTT1TIMEUP_DIS_ADDR            BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_TBTT1TIMEUP_DIS_MASK            0x00000800                // TBTT1TIMEUP_DIS[11]
#define BN0_WF_LPON_TOP_MPTCR1_TBTT1TIMEUP_DIS_SHFT            11
#define BN0_WF_LPON_TOP_MPTCR1_PREDTIM1_TRIG_DIS_ADDR          BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_PREDTIM1_TRIG_DIS_MASK          0x00000400                // PREDTIM1_TRIG_DIS[10]
#define BN0_WF_LPON_TOP_MPTCR1_PREDTIM1_TRIG_DIS_SHFT          10
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT1_TRIG_DIS_ADDR          BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT1_TRIG_DIS_MASK          0x00000200                // PRETBTT1_TRIG_DIS[9]
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT1_TRIG_DIS_SHFT          9
#define BN0_WF_LPON_TOP_MPTCR1_TBTT1PERIODTIMER_DIS_ADDR       BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_TBTT1PERIODTIMER_DIS_MASK       0x00000100                // TBTT1PERIODTIMER_DIS[8]
#define BN0_WF_LPON_TOP_MPTCR1_TBTT1PERIODTIMER_DIS_SHFT       8
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT0INT_DIS_ADDR            BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT0INT_DIS_MASK            0x00000080                // PRETBTT0INT_DIS[7]
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT0INT_DIS_SHFT            7
#define BN0_WF_LPON_TOP_MPTCR1_BMC_TIMEOUT0_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_BMC_TIMEOUT0_DIS_MASK           0x00000040                // BMC_TIMEOUT0_DIS[6]
#define BN0_WF_LPON_TOP_MPTCR1_BMC_TIMEOUT0_DIS_SHFT           6
#define BN0_WF_LPON_TOP_MPTCR1_BCN_TIMEOUT0_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_BCN_TIMEOUT0_DIS_MASK           0x00000020                // BCN_TIMEOUT0_DIS[5]
#define BN0_WF_LPON_TOP_MPTCR1_BCN_TIMEOUT0_DIS_SHFT           5
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT0TIMEUP_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT0TIMEUP_DIS_MASK         0x00000010                // PRETBTT0TIMEUP_DIS[4]
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT0TIMEUP_DIS_SHFT         4
#define BN0_WF_LPON_TOP_MPTCR1_TBTT0TIMEUP_DIS_ADDR            BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_TBTT0TIMEUP_DIS_MASK            0x00000008                // TBTT0TIMEUP_DIS[3]
#define BN0_WF_LPON_TOP_MPTCR1_TBTT0TIMEUP_DIS_SHFT            3
#define BN0_WF_LPON_TOP_MPTCR1_PREDTIM0_TRIG_DIS_ADDR          BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_PREDTIM0_TRIG_DIS_MASK          0x00000004                // PREDTIM0_TRIG_DIS[2]
#define BN0_WF_LPON_TOP_MPTCR1_PREDTIM0_TRIG_DIS_SHFT          2
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT0_TRIG_DIS_ADDR          BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT0_TRIG_DIS_MASK          0x00000002                // PRETBTT0_TRIG_DIS[1]
#define BN0_WF_LPON_TOP_MPTCR1_PRETBTT0_TRIG_DIS_SHFT          1
#define BN0_WF_LPON_TOP_MPTCR1_TBTT0PERIODTIMER_DIS_ADDR       BN0_WF_LPON_TOP_MPTCR1_ADDR
#define BN0_WF_LPON_TOP_MPTCR1_TBTT0PERIODTIMER_DIS_MASK       0x00000001                // TBTT0PERIODTIMER_DIS[0]
#define BN0_WF_LPON_TOP_MPTCR1_TBTT0PERIODTIMER_DIS_SHFT       0

/* =====================================================================================

  ---MPTCR3 (0x820EB000 + 0x304)---

    TBTT2PERIODTIMER_DIS[0]      - (WO) See MPTCR2.TBTT2PERIODTIMER_EN definition for how to disable corresponding function.
    PRETBTT2_TRIG_DIS[1]         - (WO) See MPTCR2.PRETBTT2_TRIG_EN definition for how to disable corresponding function.
    PREDTIM2_TRIG_DIS[2]         - (WO) See MPTCR2.PREDTIM2_TRIG_EN definition for how to disable corresponding function.
    TBTT2TIMEUP_DIS[3]           - (WO) See MPTCR2.TBTT2TIMEUP_EN definition for how to disable corresponding function.
    PRETBTT2TIMEUP_DIS[4]        - (WO) See MPTCR2.PRETBTT2TIMEUP_EN definition for how to disable corresponding function.
    BCN_TIMEOUT2_DIS[5]          - (WO) See MPTCR2.BCN_TIMEOUT2_EN definition for how to disable corresponding function.
    BMC_TIMEOUT2_DIS[6]          - (WO) See MPTCR2.BMC_TIMEOUT2_EN definition for how to disable corresponding function.
    PRETBTT2_INT_DIS[7]          - (WO) See MPTCR2.PRETBTT2_INT_EN definition for how to disable corresponding function.
    TBTT3PERIODTIMER_DIS[8]      - (WO) See MPTCR2.TBTT3PERIODTIMER_EN definition for how to disable corresponding function.
    PRETBTT3_TRIG_DIS[9]         - (WO) See MPTCR2.PRETBTT3_TRIG_EN definition for how to disable corresponding function.
    PREDTIM3_TRIG_DIS[10]        - (WO) See MPTCR2.PREDTIM3_TRIG_EN definition for how to disable corresponding function.
    TBTT3TIMEUP_DIS[11]          - (WO) See MPTCR2.TBTT3TIMEUP_EN definition for how to disable corresponding function.
    PRETBTT3TIMEUP_DIS[12]       - (WO) See MPTCR2.PRETBTT3TIMEUP_EN definition for how to disable corresponding function.
    BCN_TIMEOUT3_DIS[13]         - (WO) See MPTCR2.BCN_TIMEOUT3_EN definition for how to disable corresponding function.
    BMC_TIMEOUT3_DIS[14]         - (WO) See MPTCR2.BMC_TIMEOUT3_EN definition for how to disable corresponding function.
    PRETBTT3_INT_DIS[15]         - (WO) See MPTCR2.PRETBTT3_INT_EN definition for how to disable corresponding function.
    RESERVED16[26..16]           - (RO) Reserved bits
    BCN_PARSE_TIM2_DIS[27]       - (WO) See MPTCR2.BCN_PARSE_TIM2_EN definition for how to disable corresponding function.
    BCN_BMC2_DIS[28]             - (WO) See MPTCR2.BCN_BMC2_EN definition for how to disable corresponding function.
    BCN_PARSE_TIM3_DIS[29]       - (WO) See MPTCR2.BCN_PARSE_TIM3_EN definitiondefinition for how to disable corresponding function.
    BCN_BMC3_DIS[30]             - (WO) See MPTCR2.BCN_BMC3_EN definition for how to disable corresponding function.
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MPTCR3_BCN_BMC3_DIS_ADDR               BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_BCN_BMC3_DIS_MASK               0x40000000                // BCN_BMC3_DIS[30]
#define BN0_WF_LPON_TOP_MPTCR3_BCN_BMC3_DIS_SHFT               30
#define BN0_WF_LPON_TOP_MPTCR3_BCN_PARSE_TIM3_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_BCN_PARSE_TIM3_DIS_MASK         0x20000000                // BCN_PARSE_TIM3_DIS[29]
#define BN0_WF_LPON_TOP_MPTCR3_BCN_PARSE_TIM3_DIS_SHFT         29
#define BN0_WF_LPON_TOP_MPTCR3_BCN_BMC2_DIS_ADDR               BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_BCN_BMC2_DIS_MASK               0x10000000                // BCN_BMC2_DIS[28]
#define BN0_WF_LPON_TOP_MPTCR3_BCN_BMC2_DIS_SHFT               28
#define BN0_WF_LPON_TOP_MPTCR3_BCN_PARSE_TIM2_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_BCN_PARSE_TIM2_DIS_MASK         0x08000000                // BCN_PARSE_TIM2_DIS[27]
#define BN0_WF_LPON_TOP_MPTCR3_BCN_PARSE_TIM2_DIS_SHFT         27
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT3_INT_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT3_INT_DIS_MASK           0x00008000                // PRETBTT3_INT_DIS[15]
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT3_INT_DIS_SHFT           15
#define BN0_WF_LPON_TOP_MPTCR3_BMC_TIMEOUT3_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_BMC_TIMEOUT3_DIS_MASK           0x00004000                // BMC_TIMEOUT3_DIS[14]
#define BN0_WF_LPON_TOP_MPTCR3_BMC_TIMEOUT3_DIS_SHFT           14
#define BN0_WF_LPON_TOP_MPTCR3_BCN_TIMEOUT3_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_BCN_TIMEOUT3_DIS_MASK           0x00002000                // BCN_TIMEOUT3_DIS[13]
#define BN0_WF_LPON_TOP_MPTCR3_BCN_TIMEOUT3_DIS_SHFT           13
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT3TIMEUP_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT3TIMEUP_DIS_MASK         0x00001000                // PRETBTT3TIMEUP_DIS[12]
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT3TIMEUP_DIS_SHFT         12
#define BN0_WF_LPON_TOP_MPTCR3_TBTT3TIMEUP_DIS_ADDR            BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_TBTT3TIMEUP_DIS_MASK            0x00000800                // TBTT3TIMEUP_DIS[11]
#define BN0_WF_LPON_TOP_MPTCR3_TBTT3TIMEUP_DIS_SHFT            11
#define BN0_WF_LPON_TOP_MPTCR3_PREDTIM3_TRIG_DIS_ADDR          BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_PREDTIM3_TRIG_DIS_MASK          0x00000400                // PREDTIM3_TRIG_DIS[10]
#define BN0_WF_LPON_TOP_MPTCR3_PREDTIM3_TRIG_DIS_SHFT          10
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT3_TRIG_DIS_ADDR          BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT3_TRIG_DIS_MASK          0x00000200                // PRETBTT3_TRIG_DIS[9]
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT3_TRIG_DIS_SHFT          9
#define BN0_WF_LPON_TOP_MPTCR3_TBTT3PERIODTIMER_DIS_ADDR       BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_TBTT3PERIODTIMER_DIS_MASK       0x00000100                // TBTT3PERIODTIMER_DIS[8]
#define BN0_WF_LPON_TOP_MPTCR3_TBTT3PERIODTIMER_DIS_SHFT       8
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT2_INT_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT2_INT_DIS_MASK           0x00000080                // PRETBTT2_INT_DIS[7]
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT2_INT_DIS_SHFT           7
#define BN0_WF_LPON_TOP_MPTCR3_BMC_TIMEOUT2_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_BMC_TIMEOUT2_DIS_MASK           0x00000040                // BMC_TIMEOUT2_DIS[6]
#define BN0_WF_LPON_TOP_MPTCR3_BMC_TIMEOUT2_DIS_SHFT           6
#define BN0_WF_LPON_TOP_MPTCR3_BCN_TIMEOUT2_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_BCN_TIMEOUT2_DIS_MASK           0x00000020                // BCN_TIMEOUT2_DIS[5]
#define BN0_WF_LPON_TOP_MPTCR3_BCN_TIMEOUT2_DIS_SHFT           5
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT2TIMEUP_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT2TIMEUP_DIS_MASK         0x00000010                // PRETBTT2TIMEUP_DIS[4]
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT2TIMEUP_DIS_SHFT         4
#define BN0_WF_LPON_TOP_MPTCR3_TBTT2TIMEUP_DIS_ADDR            BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_TBTT2TIMEUP_DIS_MASK            0x00000008                // TBTT2TIMEUP_DIS[3]
#define BN0_WF_LPON_TOP_MPTCR3_TBTT2TIMEUP_DIS_SHFT            3
#define BN0_WF_LPON_TOP_MPTCR3_PREDTIM2_TRIG_DIS_ADDR          BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_PREDTIM2_TRIG_DIS_MASK          0x00000004                // PREDTIM2_TRIG_DIS[2]
#define BN0_WF_LPON_TOP_MPTCR3_PREDTIM2_TRIG_DIS_SHFT          2
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT2_TRIG_DIS_ADDR          BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT2_TRIG_DIS_MASK          0x00000002                // PRETBTT2_TRIG_DIS[1]
#define BN0_WF_LPON_TOP_MPTCR3_PRETBTT2_TRIG_DIS_SHFT          1
#define BN0_WF_LPON_TOP_MPTCR3_TBTT2PERIODTIMER_DIS_ADDR       BN0_WF_LPON_TOP_MPTCR3_ADDR
#define BN0_WF_LPON_TOP_MPTCR3_TBTT2PERIODTIMER_DIS_MASK       0x00000001                // TBTT2PERIODTIMER_DIS[0]
#define BN0_WF_LPON_TOP_MPTCR3_TBTT2PERIODTIMER_DIS_SHFT       0

/* =====================================================================================

  ---MPTCR5 (0x820EB000 + 0x308)---

    TTTT0PERIODTIMER_DIS[0]      - (WO) See MPTCR4.TTTT0TIMEUP_EN definition for how to disable corresponding function.
    PRETTTT0_TRIG_DIS[1]         - (WO) See MPTCR4.PRETTTT0TIMEUP_EN definition for how to disable corresponding function.
    RESERVED2[2]                 - (RO) Reserved bits
    TTTT0TIMEUP_DIS[3]           - (WO) See MPTCR4. TIM_TIMEOUT0_EN definition for how to disable corresponding function.
    PRETTTT0TIMEUP_DIS[4]        - (WO) See MPTCR4. TIM_BMC_TIMEOUT0_EN definition for how to disable corresponding function.
    TIM_TIMEOUT0_DIS[5]          - (WO) See MPTCR4.PRETTTT0INT_EN definition for how to disable corresponding function.
    BMC_TIMEOUT0_DIS[6]          - (WO) See MPTCR4. TTTT1PERIODTIMER_EN definition for how to disable corresponding function.
    PRETTTT0INT_DIS[7]           - (WO) See MPTCR4.PRETTTT0INT_EN  definition for how to disable corresponding function.
    TTTT1PERIODTIMER_DIS[8]      - (WO) See MPTCR4.PRETTTT1_TRIG_EN definition for how to disable corresponding function.
    PRETTTT1_TRIG_DIS[9]         - (WO) See MPTCR4.TTTT1TIMEUP_EN definition for how to disable corresponding function.
    RESERVED10[10]               - (RO) Reserved bits
    TTTT1TIMEUP_DIS[11]          - (WO) See MPTCR4.PRETTTT1TIMEUP_EN definition for how to disable corresponding function.
    PRETTTT1TIMEUP_DIS[12]       - (WO) See MPTCR4. TIM_TIMEOUT1_EN definition for how to disable corresponding function.
    TIM_TIMEOUT1_DIS[13]         - (WO) See MPTCR4. TIM_BMC_TIMEOUT1_EN definition for how to disable corresponding function.
    BMC_TIMEOUT1_DIS[14]         - (WO) See MPTCR4.PRETTTT1INT_EN definition for how to disable corresponding function.
    PRETTTT1INT_DIS[15]          - (WO) See MPTCR4.PRETTTT1INT_EN  definition for how to disable corresponding function.
    RESERVED16[26..16]           - (RO) Reserved bits
    TIM_PARSE_TIM0_DIS[27]       - (WO) See MPTCR4.TIM_PARSE_TIM0_EN definition for how to disable corresponding function.
    TIM_BMC0_DIS[28]             - (WO) See MPTCR4. TIM_BMC0_EN definition for how to disable corresponding function.
    TIM_PARSE_TIM1_DIS[29]       - (WO) See MPTCR4.TIM_PARSE_TIM1_EN definition for how to disable corresponding function.
    TIM_BMC1_DIS[30]             - (WO) See MPTCR4.TIM_BMC1_EN definition for how to disable corresponding function.
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MPTCR5_TIM_BMC1_DIS_ADDR               BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_TIM_BMC1_DIS_MASK               0x40000000                // TIM_BMC1_DIS[30]
#define BN0_WF_LPON_TOP_MPTCR5_TIM_BMC1_DIS_SHFT               30
#define BN0_WF_LPON_TOP_MPTCR5_TIM_PARSE_TIM1_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_TIM_PARSE_TIM1_DIS_MASK         0x20000000                // TIM_PARSE_TIM1_DIS[29]
#define BN0_WF_LPON_TOP_MPTCR5_TIM_PARSE_TIM1_DIS_SHFT         29
#define BN0_WF_LPON_TOP_MPTCR5_TIM_BMC0_DIS_ADDR               BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_TIM_BMC0_DIS_MASK               0x10000000                // TIM_BMC0_DIS[28]
#define BN0_WF_LPON_TOP_MPTCR5_TIM_BMC0_DIS_SHFT               28
#define BN0_WF_LPON_TOP_MPTCR5_TIM_PARSE_TIM0_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_TIM_PARSE_TIM0_DIS_MASK         0x08000000                // TIM_PARSE_TIM0_DIS[27]
#define BN0_WF_LPON_TOP_MPTCR5_TIM_PARSE_TIM0_DIS_SHFT         27
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT1INT_DIS_ADDR            BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT1INT_DIS_MASK            0x00008000                // PRETTTT1INT_DIS[15]
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT1INT_DIS_SHFT            15
#define BN0_WF_LPON_TOP_MPTCR5_BMC_TIMEOUT1_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_BMC_TIMEOUT1_DIS_MASK           0x00004000                // BMC_TIMEOUT1_DIS[14]
#define BN0_WF_LPON_TOP_MPTCR5_BMC_TIMEOUT1_DIS_SHFT           14
#define BN0_WF_LPON_TOP_MPTCR5_TIM_TIMEOUT1_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_TIM_TIMEOUT1_DIS_MASK           0x00002000                // TIM_TIMEOUT1_DIS[13]
#define BN0_WF_LPON_TOP_MPTCR5_TIM_TIMEOUT1_DIS_SHFT           13
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT1TIMEUP_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT1TIMEUP_DIS_MASK         0x00001000                // PRETTTT1TIMEUP_DIS[12]
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT1TIMEUP_DIS_SHFT         12
#define BN0_WF_LPON_TOP_MPTCR5_TTTT1TIMEUP_DIS_ADDR            BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_TTTT1TIMEUP_DIS_MASK            0x00000800                // TTTT1TIMEUP_DIS[11]
#define BN0_WF_LPON_TOP_MPTCR5_TTTT1TIMEUP_DIS_SHFT            11
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT1_TRIG_DIS_ADDR          BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT1_TRIG_DIS_MASK          0x00000200                // PRETTTT1_TRIG_DIS[9]
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT1_TRIG_DIS_SHFT          9
#define BN0_WF_LPON_TOP_MPTCR5_TTTT1PERIODTIMER_DIS_ADDR       BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_TTTT1PERIODTIMER_DIS_MASK       0x00000100                // TTTT1PERIODTIMER_DIS[8]
#define BN0_WF_LPON_TOP_MPTCR5_TTTT1PERIODTIMER_DIS_SHFT       8
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT0INT_DIS_ADDR            BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT0INT_DIS_MASK            0x00000080                // PRETTTT0INT_DIS[7]
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT0INT_DIS_SHFT            7
#define BN0_WF_LPON_TOP_MPTCR5_BMC_TIMEOUT0_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_BMC_TIMEOUT0_DIS_MASK           0x00000040                // BMC_TIMEOUT0_DIS[6]
#define BN0_WF_LPON_TOP_MPTCR5_BMC_TIMEOUT0_DIS_SHFT           6
#define BN0_WF_LPON_TOP_MPTCR5_TIM_TIMEOUT0_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_TIM_TIMEOUT0_DIS_MASK           0x00000020                // TIM_TIMEOUT0_DIS[5]
#define BN0_WF_LPON_TOP_MPTCR5_TIM_TIMEOUT0_DIS_SHFT           5
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT0TIMEUP_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT0TIMEUP_DIS_MASK         0x00000010                // PRETTTT0TIMEUP_DIS[4]
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT0TIMEUP_DIS_SHFT         4
#define BN0_WF_LPON_TOP_MPTCR5_TTTT0TIMEUP_DIS_ADDR            BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_TTTT0TIMEUP_DIS_MASK            0x00000008                // TTTT0TIMEUP_DIS[3]
#define BN0_WF_LPON_TOP_MPTCR5_TTTT0TIMEUP_DIS_SHFT            3
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT0_TRIG_DIS_ADDR          BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT0_TRIG_DIS_MASK          0x00000002                // PRETTTT0_TRIG_DIS[1]
#define BN0_WF_LPON_TOP_MPTCR5_PRETTTT0_TRIG_DIS_SHFT          1
#define BN0_WF_LPON_TOP_MPTCR5_TTTT0PERIODTIMER_DIS_ADDR       BN0_WF_LPON_TOP_MPTCR5_ADDR
#define BN0_WF_LPON_TOP_MPTCR5_TTTT0PERIODTIMER_DIS_MASK       0x00000001                // TTTT0PERIODTIMER_DIS[0]
#define BN0_WF_LPON_TOP_MPTCR5_TTTT0PERIODTIMER_DIS_SHFT       0

/* =====================================================================================

  ---MPTCR7 (0x820EB000 + 0x30c)---

    TTTT2PERIODTIMER_DIS[0]      - (WO) See MPTCR6.TTTT2TIMEUP_EN definition for how to disable corresponding function.
    PRETTTT2_TRIG_DIS[1]         - (WO) See MPTCR6.PRETTTT2TIMEUP_EN definition for how to disable corresponding function.
    RESERVED2[2]                 - (RO) Reserved bits
    TTTT2TIMEUP_DIS[3]           - (WO) See MPTCR6. TIM_TIMEOUT2_EN definition for how to disable corresponding function.
    PRETTTT2TIMEUP_DIS[4]        - (WO) See MPTCR6. TIM_BMC_TIMEOUT2_EN definition for how to disable corresponding function.
    TIM_TIMEOUT2_DIS[5]          - (WO) See MPTCR6.PRETTTT2INT_EN definition for how to disable corresponding function.
    BMC_TIMEOUT2_DIS[6]          - (WO) See MPTCR6. TTTT3PERIODTIMER_EN definition for how to disable corresponding function.
    PRETTTT2INT_DIS[7]           - (WO) See MPTCR6.PRETTTT3INT_EN  definition for how to disable corresponding function.
    TTTT3PERIODTIMER_DIS[8]      - (WO) See MPTCR6.PRETTTT3_TRIG_EN definition for how to disable corresponding function.
    PRETTTT3_TRIG_DIS[9]         - (WO) See MPTCR6.TTTT2TIMEUP_EN definition for how to disable corresponding function.
    RESERVED10[10]               - (RO) Reserved bits
    TTTT3TIMEUP_DIS[11]          - (WO) See MPTCR6.PRETTTT3TIMEUP_EN definition for how to disable corresponding function.
    PRETTTT3TIMEUP_DIS[12]       - (WO) See MPTCR6. TIM_TIMEOUT3_EN definition for how to disable corresponding function.
    TIM_TIMEOUT3_DIS[13]         - (WO) See MPTCR6. TIM_BMC_TIMEOUT3_EN definition for how to disable corresponding function.
    BMC_TIMEOUT3_DIS[14]         - (WO) See MPTCR6.PRETTTT3INT_EN definition for how to disable corresponding function.
    PRETTTT3INT_DIS[15]          - (WO) See MPTCR6.PRETTTT3INT_EN  definition for how to disable corresponding function.
    RESERVED16[26..16]           - (RO) Reserved bits
    TIM_PARSE_TIM2_DIS[27]       - (WO) See MPTCR6.TIM_PARSE_TIM2_EN definition for how to disable corresponding function.
    TIM_BMC2_DIS[28]             - (WO) See MPTCR6. TIM_BMC2_EN definition for how to disable corresponding function.
    TIM_PARSE_TIM3_DIS[29]       - (WO) See MPTCR6.TIM_PARSE_TIM3_EN definition for how to disable corresponding function.
    TIM_BMC3_DIS[30]             - (WO) See MPTCR6.TIM_BMC3_EN definition for how to disable corresponding function.
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MPTCR7_TIM_BMC3_DIS_ADDR               BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_TIM_BMC3_DIS_MASK               0x40000000                // TIM_BMC3_DIS[30]
#define BN0_WF_LPON_TOP_MPTCR7_TIM_BMC3_DIS_SHFT               30
#define BN0_WF_LPON_TOP_MPTCR7_TIM_PARSE_TIM3_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_TIM_PARSE_TIM3_DIS_MASK         0x20000000                // TIM_PARSE_TIM3_DIS[29]
#define BN0_WF_LPON_TOP_MPTCR7_TIM_PARSE_TIM3_DIS_SHFT         29
#define BN0_WF_LPON_TOP_MPTCR7_TIM_BMC2_DIS_ADDR               BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_TIM_BMC2_DIS_MASK               0x10000000                // TIM_BMC2_DIS[28]
#define BN0_WF_LPON_TOP_MPTCR7_TIM_BMC2_DIS_SHFT               28
#define BN0_WF_LPON_TOP_MPTCR7_TIM_PARSE_TIM2_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_TIM_PARSE_TIM2_DIS_MASK         0x08000000                // TIM_PARSE_TIM2_DIS[27]
#define BN0_WF_LPON_TOP_MPTCR7_TIM_PARSE_TIM2_DIS_SHFT         27
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT3INT_DIS_ADDR            BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT3INT_DIS_MASK            0x00008000                // PRETTTT3INT_DIS[15]
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT3INT_DIS_SHFT            15
#define BN0_WF_LPON_TOP_MPTCR7_BMC_TIMEOUT3_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_BMC_TIMEOUT3_DIS_MASK           0x00004000                // BMC_TIMEOUT3_DIS[14]
#define BN0_WF_LPON_TOP_MPTCR7_BMC_TIMEOUT3_DIS_SHFT           14
#define BN0_WF_LPON_TOP_MPTCR7_TIM_TIMEOUT3_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_TIM_TIMEOUT3_DIS_MASK           0x00002000                // TIM_TIMEOUT3_DIS[13]
#define BN0_WF_LPON_TOP_MPTCR7_TIM_TIMEOUT3_DIS_SHFT           13
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT3TIMEUP_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT3TIMEUP_DIS_MASK         0x00001000                // PRETTTT3TIMEUP_DIS[12]
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT3TIMEUP_DIS_SHFT         12
#define BN0_WF_LPON_TOP_MPTCR7_TTTT3TIMEUP_DIS_ADDR            BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_TTTT3TIMEUP_DIS_MASK            0x00000800                // TTTT3TIMEUP_DIS[11]
#define BN0_WF_LPON_TOP_MPTCR7_TTTT3TIMEUP_DIS_SHFT            11
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT3_TRIG_DIS_ADDR          BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT3_TRIG_DIS_MASK          0x00000200                // PRETTTT3_TRIG_DIS[9]
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT3_TRIG_DIS_SHFT          9
#define BN0_WF_LPON_TOP_MPTCR7_TTTT3PERIODTIMER_DIS_ADDR       BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_TTTT3PERIODTIMER_DIS_MASK       0x00000100                // TTTT3PERIODTIMER_DIS[8]
#define BN0_WF_LPON_TOP_MPTCR7_TTTT3PERIODTIMER_DIS_SHFT       8
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT2INT_DIS_ADDR            BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT2INT_DIS_MASK            0x00000080                // PRETTTT2INT_DIS[7]
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT2INT_DIS_SHFT            7
#define BN0_WF_LPON_TOP_MPTCR7_BMC_TIMEOUT2_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_BMC_TIMEOUT2_DIS_MASK           0x00000040                // BMC_TIMEOUT2_DIS[6]
#define BN0_WF_LPON_TOP_MPTCR7_BMC_TIMEOUT2_DIS_SHFT           6
#define BN0_WF_LPON_TOP_MPTCR7_TIM_TIMEOUT2_DIS_ADDR           BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_TIM_TIMEOUT2_DIS_MASK           0x00000020                // TIM_TIMEOUT2_DIS[5]
#define BN0_WF_LPON_TOP_MPTCR7_TIM_TIMEOUT2_DIS_SHFT           5
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT2TIMEUP_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT2TIMEUP_DIS_MASK         0x00000010                // PRETTTT2TIMEUP_DIS[4]
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT2TIMEUP_DIS_SHFT         4
#define BN0_WF_LPON_TOP_MPTCR7_TTTT2TIMEUP_DIS_ADDR            BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_TTTT2TIMEUP_DIS_MASK            0x00000008                // TTTT2TIMEUP_DIS[3]
#define BN0_WF_LPON_TOP_MPTCR7_TTTT2TIMEUP_DIS_SHFT            3
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT2_TRIG_DIS_ADDR          BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT2_TRIG_DIS_MASK          0x00000002                // PRETTTT2_TRIG_DIS[1]
#define BN0_WF_LPON_TOP_MPTCR7_PRETTTT2_TRIG_DIS_SHFT          1
#define BN0_WF_LPON_TOP_MPTCR7_TTTT2PERIODTIMER_DIS_ADDR       BN0_WF_LPON_TOP_MPTCR7_ADDR
#define BN0_WF_LPON_TOP_MPTCR7_TTTT2PERIODTIMER_DIS_MASK       0x00000001                // TTTT2PERIODTIMER_DIS[0]
#define BN0_WF_LPON_TOP_MPTCR7_TTTT2PERIODTIMER_DIS_SHFT       0

/* =====================================================================================

  ---MPTCR9 (0x820EB000 + 0x310)---

    TWT0TIMER_DIS[0]             - (WO) See MPTCR8. TWT0TIMER_EN definition for how to disable corresponding function.
    TWT0TIMER_INT_DIS[1]         - (WO) See MPTCR8. TWT0TIMER_INT_EN definition for how to disable corresponding function.
    RESERVED2[7..2]              - (RO) Reserved bits
    TWT1TIMER_DIS[8]             - (WO) See MPTCR8. TWT1TIMER_EN definition for how to disable corresponding function.
    TWT1TIMER_INT_DIS[9]         - (WO) See MPTCR8. TWT1TIMER_INT_EN definition for how to disable corresponding function.
    RESERVED10[15..10]           - (RO) Reserved bits
    MU_EDCA0_TIMER_DIS[16]       - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.
    MU_EDCA1_TIMER_DIS[17]       - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.
    MU_EDCA2_TIMER_DIS[18]       - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.
    MU_EDCA3_TIMER_DIS[19]       - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.
    MU_EDCA4_TIMER_DIS[20]       - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.
    MU_EDCA5_TIMER_DIS[21]       - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.
    MU_EDCA6_TIMER_DIS[22]       - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.
    MU_EDCA7_TIMER_DIS[23]       - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.
    MU_EDCA8_TIMER_DIS[24]       - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.
    MU_EDCA9_TIMER_DIS[25]       - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.
    MU_EDCA10_TIMER_DIS[26]      - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.
    MU_EDCA11_TIMER_DIS[27]      - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.
    MU_EDCA12_TIMER_DIS[28]      - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.
    MU_EDCA13_TIMER_DIS[29]      - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.
    MU_EDCA14_TIMER_DIS[30]      - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.
    MU_EDCA15_TIMER_DIS[31]      - (WO) See MPTCR8. MU_EDCATIMER_EN definition for how to disable corresponding function.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA15_TIMER_DIS_ADDR        BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA15_TIMER_DIS_MASK        0x80000000                // MU_EDCA15_TIMER_DIS[31]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA15_TIMER_DIS_SHFT        31
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA14_TIMER_DIS_ADDR        BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA14_TIMER_DIS_MASK        0x40000000                // MU_EDCA14_TIMER_DIS[30]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA14_TIMER_DIS_SHFT        30
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA13_TIMER_DIS_ADDR        BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA13_TIMER_DIS_MASK        0x20000000                // MU_EDCA13_TIMER_DIS[29]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA13_TIMER_DIS_SHFT        29
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA12_TIMER_DIS_ADDR        BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA12_TIMER_DIS_MASK        0x10000000                // MU_EDCA12_TIMER_DIS[28]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA12_TIMER_DIS_SHFT        28
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA11_TIMER_DIS_ADDR        BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA11_TIMER_DIS_MASK        0x08000000                // MU_EDCA11_TIMER_DIS[27]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA11_TIMER_DIS_SHFT        27
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA10_TIMER_DIS_ADDR        BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA10_TIMER_DIS_MASK        0x04000000                // MU_EDCA10_TIMER_DIS[26]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA10_TIMER_DIS_SHFT        26
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA9_TIMER_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA9_TIMER_DIS_MASK         0x02000000                // MU_EDCA9_TIMER_DIS[25]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA9_TIMER_DIS_SHFT         25
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA8_TIMER_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA8_TIMER_DIS_MASK         0x01000000                // MU_EDCA8_TIMER_DIS[24]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA8_TIMER_DIS_SHFT         24
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA7_TIMER_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA7_TIMER_DIS_MASK         0x00800000                // MU_EDCA7_TIMER_DIS[23]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA7_TIMER_DIS_SHFT         23
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA6_TIMER_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA6_TIMER_DIS_MASK         0x00400000                // MU_EDCA6_TIMER_DIS[22]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA6_TIMER_DIS_SHFT         22
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA5_TIMER_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA5_TIMER_DIS_MASK         0x00200000                // MU_EDCA5_TIMER_DIS[21]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA5_TIMER_DIS_SHFT         21
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA4_TIMER_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA4_TIMER_DIS_MASK         0x00100000                // MU_EDCA4_TIMER_DIS[20]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA4_TIMER_DIS_SHFT         20
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA3_TIMER_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA3_TIMER_DIS_MASK         0x00080000                // MU_EDCA3_TIMER_DIS[19]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA3_TIMER_DIS_SHFT         19
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA2_TIMER_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA2_TIMER_DIS_MASK         0x00040000                // MU_EDCA2_TIMER_DIS[18]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA2_TIMER_DIS_SHFT         18
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA1_TIMER_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA1_TIMER_DIS_MASK         0x00020000                // MU_EDCA1_TIMER_DIS[17]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA1_TIMER_DIS_SHFT         17
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA0_TIMER_DIS_ADDR         BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA0_TIMER_DIS_MASK         0x00010000                // MU_EDCA0_TIMER_DIS[16]
#define BN0_WF_LPON_TOP_MPTCR9_MU_EDCA0_TIMER_DIS_SHFT         16
#define BN0_WF_LPON_TOP_MPTCR9_TWT1TIMER_INT_DIS_ADDR          BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_TWT1TIMER_INT_DIS_MASK          0x00000200                // TWT1TIMER_INT_DIS[9]
#define BN0_WF_LPON_TOP_MPTCR9_TWT1TIMER_INT_DIS_SHFT          9
#define BN0_WF_LPON_TOP_MPTCR9_TWT1TIMER_DIS_ADDR              BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_TWT1TIMER_DIS_MASK              0x00000100                // TWT1TIMER_DIS[8]
#define BN0_WF_LPON_TOP_MPTCR9_TWT1TIMER_DIS_SHFT              8
#define BN0_WF_LPON_TOP_MPTCR9_TWT0TIMER_INT_DIS_ADDR          BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_TWT0TIMER_INT_DIS_MASK          0x00000002                // TWT0TIMER_INT_DIS[1]
#define BN0_WF_LPON_TOP_MPTCR9_TWT0TIMER_INT_DIS_SHFT          1
#define BN0_WF_LPON_TOP_MPTCR9_TWT0TIMER_DIS_ADDR              BN0_WF_LPON_TOP_MPTCR9_ADDR
#define BN0_WF_LPON_TOP_MPTCR9_TWT0TIMER_DIS_MASK              0x00000001                // TWT0TIMER_DIS[0]
#define BN0_WF_LPON_TOP_MPTCR9_TWT0TIMER_DIS_SHFT              0

/* =====================================================================================

  ---FRCR (0x820EB000 + 0x0314)---

    COUNTER[31..0]               - (RU) Free-run counter which starts counting from WiFiSYS power ON or reset
                                     Unit: 1us
                                     When working under slow clock, it will compensate for the slow clock count width.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_FRCR_COUNTER_ADDR                      BN0_WF_LPON_TOP_FRCR_ADDR
#define BN0_WF_LPON_TOP_FRCR_COUNTER_MASK                      0xFFFFFFFF                // COUNTER[31..0]
#define BN0_WF_LPON_TOP_FRCR_COUNTER_SHFT                      0

/* =====================================================================================

  ---MMCR0 (0x820EB000 + 0x318)---

    MEASURE_DURATION0[15..0]     - (RW) Duration of each measurement interval
                                     Unit: TU
    MEASURE_REQ0[16]             - (RU) Set Measure Request 0
    RESERVED17[18..17]           - (RO) Reserved bits
    FPGA_CON_TST[19]             - (RW) When set to 1, this is used for FPGA test only. Otherwise, it follows normal measurement rule.
    LP_CR_WIFI_BYPASS_MEASURE0_SEL[21..20] - (RW) Decides if measurement 0 bypasses the time reserved for BT/WIMAX
                                     2'b00: Not bypass
                                     2'b01: Bypass the time only when BT in TX/RX
                                     2'b10: Bypass the time when BT in TX/RX or PTA sets WIFI remain windows = 0
                                     2'b11: Reserved
    FPGA_MEASURE_EN[25..22]      - (RW) For measurement enabled by FPGA_CON_TST set to 1, one hot encoding, 4'b0001/0010/0100/1000 presents BSSID0/1/2/3 respectively.
    BSS_REQUEST[29..26]          - (RW) Issues TSF time comparison request to MT7615 WIFI
                                     If there is any new command to set up, software driver will need to disable the old command if the previous command is still active.
                                     Write:
                                     4'b0000: Disable. If there is previous TSF comparison request running, MT7615 WIFI will stop the old operation.
                                     4'b0001/0010/0100/1000: Enable. When enabled, MT7615 WIFI will reset MMCR0.BSS start BSS measurement when the local TSF[31:0] equals MMCR1/MMCR2.Measure_TSF_Time. After MMCR3.Duration time has passed, MT7615 WIFI will stop BSS measurement and set WISR.Measurement_Done to 1. 
                                     4'b1111: Always enable this function for measurement, regardless of Measure_TSF_Time.
                                     When local TSF[0:31] equals MMCR1/MMCR2.Measure_TSF_Time but the MMCR3.Duration time is set to 0, MT7615 will set WISR.Measurement_Done to 1 directly.
    BSS[30]                      - (RU) Result of BSS request measurement
                                     When this bit is set by MAC, it indicates there is at least one valid MPDU (not including probe request frame) received in the channel during the measurement period from another BSS or IBSS. 
                                     This bit will be cleared first when BSS_Request is set or this bit will be written 1.
    MEASUREMENT_SKIP0[31]        - (W1C) Indicates the measurement start time or end time are skipped due to TSF time drift
                                     MAC will assert this bit if TSF does not match MMCR1.Measure_TSF_Time or End time due to TSF drift.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MMCR0_MEASUREMENT_SKIP0_ADDR           BN0_WF_LPON_TOP_MMCR0_ADDR
#define BN0_WF_LPON_TOP_MMCR0_MEASUREMENT_SKIP0_MASK           0x80000000                // MEASUREMENT_SKIP0[31]
#define BN0_WF_LPON_TOP_MMCR0_MEASUREMENT_SKIP0_SHFT           31
#define BN0_WF_LPON_TOP_MMCR0_BSS_ADDR                         BN0_WF_LPON_TOP_MMCR0_ADDR
#define BN0_WF_LPON_TOP_MMCR0_BSS_MASK                         0x40000000                // BSS[30]
#define BN0_WF_LPON_TOP_MMCR0_BSS_SHFT                         30
#define BN0_WF_LPON_TOP_MMCR0_BSS_REQUEST_ADDR                 BN0_WF_LPON_TOP_MMCR0_ADDR
#define BN0_WF_LPON_TOP_MMCR0_BSS_REQUEST_MASK                 0x3C000000                // BSS_REQUEST[29..26]
#define BN0_WF_LPON_TOP_MMCR0_BSS_REQUEST_SHFT                 26
#define BN0_WF_LPON_TOP_MMCR0_FPGA_MEASURE_EN_ADDR             BN0_WF_LPON_TOP_MMCR0_ADDR
#define BN0_WF_LPON_TOP_MMCR0_FPGA_MEASURE_EN_MASK             0x03C00000                // FPGA_MEASURE_EN[25..22]
#define BN0_WF_LPON_TOP_MMCR0_FPGA_MEASURE_EN_SHFT             22
#define BN0_WF_LPON_TOP_MMCR0_LP_CR_WIFI_BYPASS_MEASURE0_SEL_ADDR BN0_WF_LPON_TOP_MMCR0_ADDR
#define BN0_WF_LPON_TOP_MMCR0_LP_CR_WIFI_BYPASS_MEASURE0_SEL_MASK 0x00300000                // LP_CR_WIFI_BYPASS_MEASURE0_SEL[21..20]
#define BN0_WF_LPON_TOP_MMCR0_LP_CR_WIFI_BYPASS_MEASURE0_SEL_SHFT 20
#define BN0_WF_LPON_TOP_MMCR0_FPGA_CON_TST_ADDR                BN0_WF_LPON_TOP_MMCR0_ADDR
#define BN0_WF_LPON_TOP_MMCR0_FPGA_CON_TST_MASK                0x00080000                // FPGA_CON_TST[19]
#define BN0_WF_LPON_TOP_MMCR0_FPGA_CON_TST_SHFT                19
#define BN0_WF_LPON_TOP_MMCR0_MEASURE_REQ0_ADDR                BN0_WF_LPON_TOP_MMCR0_ADDR
#define BN0_WF_LPON_TOP_MMCR0_MEASURE_REQ0_MASK                0x00010000                // MEASURE_REQ0[16]
#define BN0_WF_LPON_TOP_MMCR0_MEASURE_REQ0_SHFT                16
#define BN0_WF_LPON_TOP_MMCR0_MEASURE_DURATION0_ADDR           BN0_WF_LPON_TOP_MMCR0_ADDR
#define BN0_WF_LPON_TOP_MMCR0_MEASURE_DURATION0_MASK           0x0000FFFF                // MEASURE_DURATION0[15..0]
#define BN0_WF_LPON_TOP_MMCR0_MEASURE_DURATION0_SHFT           0

/* =====================================================================================

  ---MMCR1 (0x820EB000 + 0x31c)---

    MEASURE_TSF0_TIME[31..0]     - (RW) When the local TSF0[31:0] matches this field, MT7615 WIFI will start the measurement processing.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MMCR1_MEASURE_TSF0_TIME_ADDR           BN0_WF_LPON_TOP_MMCR1_ADDR
#define BN0_WF_LPON_TOP_MMCR1_MEASURE_TSF0_TIME_MASK           0xFFFFFFFF                // MEASURE_TSF0_TIME[31..0]
#define BN0_WF_LPON_TOP_MMCR1_MEASURE_TSF0_TIME_SHFT           0

/* =====================================================================================

  ---MMCR2 (0x820EB000 + 0x320)---

    MEASURE_DURATION1[15..0]     - (RW) Duration of each measurement interval
                                     Unit: TU
    MEASURE_REQ1[16]             - (RU) Set Measure Request 1
    RESERVED17[19..17]           - (RO) Reserved bits
    LP_CR_WIFI_BYPASS_MEASURE1_SEL[21..20] - (RW) Decides if measurement 1 bypasses the time reserved for BT/WIMAX
                                     2'b00: Not bypass
                                     2'b01: Bypass the time only when BT in TX/RX
                                     2'b10: Bypass the time when BT in TX/RX or PTA sets WIFI remain windows = 0
                                     2'b11: Reserved
    RESERVED22[30..22]           - (RO) Reserved bits
    MEASUREMENT_SKIP1[31]        - (W1C) Indicates the measurement start time or end time are skipped due to TSF time drift
                                     MAC will assert this bit if TSF does not match MMCR3.Measure_TSF_Time or End time due to TSF drift.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MMCR2_MEASUREMENT_SKIP1_ADDR           BN0_WF_LPON_TOP_MMCR2_ADDR
#define BN0_WF_LPON_TOP_MMCR2_MEASUREMENT_SKIP1_MASK           0x80000000                // MEASUREMENT_SKIP1[31]
#define BN0_WF_LPON_TOP_MMCR2_MEASUREMENT_SKIP1_SHFT           31
#define BN0_WF_LPON_TOP_MMCR2_LP_CR_WIFI_BYPASS_MEASURE1_SEL_ADDR BN0_WF_LPON_TOP_MMCR2_ADDR
#define BN0_WF_LPON_TOP_MMCR2_LP_CR_WIFI_BYPASS_MEASURE1_SEL_MASK 0x00300000                // LP_CR_WIFI_BYPASS_MEASURE1_SEL[21..20]
#define BN0_WF_LPON_TOP_MMCR2_LP_CR_WIFI_BYPASS_MEASURE1_SEL_SHFT 20
#define BN0_WF_LPON_TOP_MMCR2_MEASURE_REQ1_ADDR                BN0_WF_LPON_TOP_MMCR2_ADDR
#define BN0_WF_LPON_TOP_MMCR2_MEASURE_REQ1_MASK                0x00010000                // MEASURE_REQ1[16]
#define BN0_WF_LPON_TOP_MMCR2_MEASURE_REQ1_SHFT                16
#define BN0_WF_LPON_TOP_MMCR2_MEASURE_DURATION1_ADDR           BN0_WF_LPON_TOP_MMCR2_ADDR
#define BN0_WF_LPON_TOP_MMCR2_MEASURE_DURATION1_MASK           0x0000FFFF                // MEASURE_DURATION1[15..0]
#define BN0_WF_LPON_TOP_MMCR2_MEASURE_DURATION1_SHFT           0

/* =====================================================================================

  ---MMCR3 (0x820EB000 + 0x324)---

    MEASURE_TSF1_TIME[31..0]     - (RW) When the local TSF1[31:0] matches this field, MT7615 WIFI will start the measurement processing.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MMCR3_MEASURE_TSF1_TIME_ADDR           BN0_WF_LPON_TOP_MMCR3_ADDR
#define BN0_WF_LPON_TOP_MMCR3_MEASURE_TSF1_TIME_MASK           0xFFFFFFFF                // MEASURE_TSF1_TIME[31..0]
#define BN0_WF_LPON_TOP_MMCR3_MEASURE_TSF1_TIME_SHFT           0

/* =====================================================================================

  ---MMBSR0 (0x820EB000 + 0x328)---

    MEASURE_BYPASS_TIME0[23..0]  - (RC) Measurement 0 bypass time
                                     Unit: us
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MMBSR0_MEASURE_BYPASS_TIME0_ADDR       BN0_WF_LPON_TOP_MMBSR0_ADDR
#define BN0_WF_LPON_TOP_MMBSR0_MEASURE_BYPASS_TIME0_MASK       0x00FFFFFF                // MEASURE_BYPASS_TIME0[23..0]
#define BN0_WF_LPON_TOP_MMBSR0_MEASURE_BYPASS_TIME0_SHFT       0

/* =====================================================================================

  ---MMBSR1 (0x820EB000 + 0x32c)---

    MEASURE_BYPASS_TIME1[23..0]  - (RC) Measurement 1 bypass time in unit of us
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MMBSR1_MEASURE_BYPASS_TIME1_ADDR       BN0_WF_LPON_TOP_MMBSR1_ADDR
#define BN0_WF_LPON_TOP_MMBSR1_MEASURE_BYPASS_TIME1_MASK       0x00FFFFFF                // MEASURE_BYPASS_TIME1[23..0]
#define BN0_WF_LPON_TOP_MMBSR1_MEASURE_BYPASS_TIME1_SHFT       0

/* =====================================================================================

  ---MMCR4 (0x820EB000 + 0x330)---

    MEASURE_DURATION2[15..0]     - (RW) Duration of each measurement interval
                                     Unit: TU
    MEASURE_REQ2[16]             - (RU)  xxx 
    RESERVED17[19..17]           - (RO) Reserved bits
    LP_CR_WIFI_BYPASS_MEASURE2_SEL[21..20] - (RW) Decides if measurement 0 bypasses the time reserved for BT/WIMAX
                                     2'b00: Not bypass
                                     2'b01: Bypass the time only when BT in TX/RX
                                     2'b10: Bypass the time when BT in TX/RX or PTA sets WIFI remain windows = 0
                                     2'b11: Reserved
    RESERVED22[30..22]           - (RO) Reserved bits
    MEASUREMENT_SKIP2[31]        - (W1C) Indicates measurement start time or end time are skipped due to TSF time drift
                                     MAC will assert this bit if TSF does not match MMCR5.Measure_TSF_Time or End time due to TSF drift.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MMCR4_MEASUREMENT_SKIP2_ADDR           BN0_WF_LPON_TOP_MMCR4_ADDR
#define BN0_WF_LPON_TOP_MMCR4_MEASUREMENT_SKIP2_MASK           0x80000000                // MEASUREMENT_SKIP2[31]
#define BN0_WF_LPON_TOP_MMCR4_MEASUREMENT_SKIP2_SHFT           31
#define BN0_WF_LPON_TOP_MMCR4_LP_CR_WIFI_BYPASS_MEASURE2_SEL_ADDR BN0_WF_LPON_TOP_MMCR4_ADDR
#define BN0_WF_LPON_TOP_MMCR4_LP_CR_WIFI_BYPASS_MEASURE2_SEL_MASK 0x00300000                // LP_CR_WIFI_BYPASS_MEASURE2_SEL[21..20]
#define BN0_WF_LPON_TOP_MMCR4_LP_CR_WIFI_BYPASS_MEASURE2_SEL_SHFT 20
#define BN0_WF_LPON_TOP_MMCR4_MEASURE_REQ2_ADDR                BN0_WF_LPON_TOP_MMCR4_ADDR
#define BN0_WF_LPON_TOP_MMCR4_MEASURE_REQ2_MASK                0x00010000                // MEASURE_REQ2[16]
#define BN0_WF_LPON_TOP_MMCR4_MEASURE_REQ2_SHFT                16
#define BN0_WF_LPON_TOP_MMCR4_MEASURE_DURATION2_ADDR           BN0_WF_LPON_TOP_MMCR4_ADDR
#define BN0_WF_LPON_TOP_MMCR4_MEASURE_DURATION2_MASK           0x0000FFFF                // MEASURE_DURATION2[15..0]
#define BN0_WF_LPON_TOP_MMCR4_MEASURE_DURATION2_SHFT           0

/* =====================================================================================

  ---MMCR5 (0x820EB000 + 0x334)---

    MEASURE_TSF2_TIME[31..0]     - (RW) When the local TSF2[31:0] matches to this field, MT7615 WIFI will start the measurement processing

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MMCR5_MEASURE_TSF2_TIME_ADDR           BN0_WF_LPON_TOP_MMCR5_ADDR
#define BN0_WF_LPON_TOP_MMCR5_MEASURE_TSF2_TIME_MASK           0xFFFFFFFF                // MEASURE_TSF2_TIME[31..0]
#define BN0_WF_LPON_TOP_MMCR5_MEASURE_TSF2_TIME_SHFT           0

/* =====================================================================================

  ---MMCR6 (0x820EB000 + 0x338)---

    MEASURE_DURATION3[15..0]     - (RW) Duration of each measurement interval
                                     Unit: TU
    MEASURE_REQ3[16]             - (RU) Set Measure Request 3
    RESERVED17[19..17]           - (RO) Reserved bits
    LP_CR_WIFI_BYPASS_MEASURE3_SEL[21..20] - (RW) Decides if measurement 1 bypasses the time reserved for BT/WIMAX
                                     2'b00: Not bypass
                                     2'b01: Bypass the time only when BT in TX/RX
                                     2'b10: Bypass the time when BT in TX/RX or PTA sets WIFI remain windows = 0
                                     2'b11: Reserved
    RESERVED22[30..22]           - (RO) Reserved bits
    MEASUREMENT_SKIP3[31]        - (W1C) Indicates measurement start time or end time are skipped due to TSF time drift
                                     MAC will assert this bit if TSF does not match MMCR7.Measure_TSF_Time or End time due to TSF drift.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MMCR6_MEASUREMENT_SKIP3_ADDR           BN0_WF_LPON_TOP_MMCR6_ADDR
#define BN0_WF_LPON_TOP_MMCR6_MEASUREMENT_SKIP3_MASK           0x80000000                // MEASUREMENT_SKIP3[31]
#define BN0_WF_LPON_TOP_MMCR6_MEASUREMENT_SKIP3_SHFT           31
#define BN0_WF_LPON_TOP_MMCR6_LP_CR_WIFI_BYPASS_MEASURE3_SEL_ADDR BN0_WF_LPON_TOP_MMCR6_ADDR
#define BN0_WF_LPON_TOP_MMCR6_LP_CR_WIFI_BYPASS_MEASURE3_SEL_MASK 0x00300000                // LP_CR_WIFI_BYPASS_MEASURE3_SEL[21..20]
#define BN0_WF_LPON_TOP_MMCR6_LP_CR_WIFI_BYPASS_MEASURE3_SEL_SHFT 20
#define BN0_WF_LPON_TOP_MMCR6_MEASURE_REQ3_ADDR                BN0_WF_LPON_TOP_MMCR6_ADDR
#define BN0_WF_LPON_TOP_MMCR6_MEASURE_REQ3_MASK                0x00010000                // MEASURE_REQ3[16]
#define BN0_WF_LPON_TOP_MMCR6_MEASURE_REQ3_SHFT                16
#define BN0_WF_LPON_TOP_MMCR6_MEASURE_DURATION3_ADDR           BN0_WF_LPON_TOP_MMCR6_ADDR
#define BN0_WF_LPON_TOP_MMCR6_MEASURE_DURATION3_MASK           0x0000FFFF                // MEASURE_DURATION3[15..0]
#define BN0_WF_LPON_TOP_MMCR6_MEASURE_DURATION3_SHFT           0

/* =====================================================================================

  ---MMCR7 (0x820EB000 + 0x33c)---

    MEASURE_TSF3_TIME[31..0]     - (RW) When the local TSF3[31:0] matches this field, MT7615 WIFI will start the measurement processing.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MMCR7_MEASURE_TSF3_TIME_ADDR           BN0_WF_LPON_TOP_MMCR7_ADDR
#define BN0_WF_LPON_TOP_MMCR7_MEASURE_TSF3_TIME_MASK           0xFFFFFFFF                // MEASURE_TSF3_TIME[31..0]
#define BN0_WF_LPON_TOP_MMCR7_MEASURE_TSF3_TIME_SHFT           0

/* =====================================================================================

  ---MMBSR2 (0x820EB000 + 0x340)---

    MEASURE_BYPASS_TIME2[23..0]  - (RC) Measurement 2 bypass time
                                     Unit: us
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MMBSR2_MEASURE_BYPASS_TIME2_ADDR       BN0_WF_LPON_TOP_MMBSR2_ADDR
#define BN0_WF_LPON_TOP_MMBSR2_MEASURE_BYPASS_TIME2_MASK       0x00FFFFFF                // MEASURE_BYPASS_TIME2[23..0]
#define BN0_WF_LPON_TOP_MMBSR2_MEASURE_BYPASS_TIME2_SHFT       0

/* =====================================================================================

  ---MMBSR3 (0x820EB000 + 0x344)---

    MEASURE_BYPASS_TIME3[23..0]  - (RC) Measurement 3 bypass time
                                     Unit: us
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_LPON_TOP_MMBSR3_MEASURE_BYPASS_TIME3_ADDR       BN0_WF_LPON_TOP_MMBSR3_ADDR
#define BN0_WF_LPON_TOP_MMBSR3_MEASURE_BYPASS_TIME3_MASK       0x00FFFFFF                // MEASURE_BYPASS_TIME3[23..0]
#define BN0_WF_LPON_TOP_MMBSR3_MEASURE_BYPASS_TIME3_SHFT       0

/* =====================================================================================

  ---QCCR0 (0x820EB000 + 0x348)---

    QUIET_TSF_TIME[15..0]        - (RW) When the local TSF[25:10] matches this field, MAC will start the quiet processing. 
                                     FW will calculate the target TSF time for starting the next quiet period. If the next quiet period start time is longer than 2^16 (longer than this field can address), use a software timer set to (2^16-1000)TU then send a probe request to get new quiet information when timeout.
                                     During quiet, ACK will still be responded, but it will not meet the requirement of 802.11h spec.
    RESERVED16[28..16]           - (RO) Reserved bits
    QUIET_SOURCE_SEL[30..29]     - (RW) Selects quiet timer source
                                     2'b00: BSSID0 TSF timer
                                     2'b01: BSSID1 TSF timer
                                     2'b10: BSSID2 TSF timer
                                     2'b11: BSSID3 TSF timer
    QUIET_EN[31]                 - (RW) Enables quiet procedure
                                     0: Disable. MT7615 WIFI can transmit frame.
                                     1: Enable. MT7615 WIFI will stop transmitting frames for a QCCR1.Duration when the local TSF[25:10] matches QCCR0.QUIET_TSF_TIME, and WISR.Quiet_Done will be generated when the duration value is down counted to 0. If software driver sets QCCR1.Duration = 0 and QCCR0.QUIET_EN = 1, WISR.Quiet_Done will be generated when the local TSF[25:10] matches QCCR0.QUIET_TSF_TIME. If there is any new quiet function to be set when the previous quiet function is still active, software driver should disable the old one and set up new command to MAC. ACK frame that can be transmitted even when  QUIET_EN is asserted.
                                     After completing the quiet procedure, MAC will reset this bit to 0.

 =====================================================================================*/
#define BN0_WF_LPON_TOP_QCCR0_QUIET_EN_ADDR                    BN0_WF_LPON_TOP_QCCR0_ADDR
#define BN0_WF_LPON_TOP_QCCR0_QUIET_EN_MASK                    0x80000000                // QUIET_EN[31]
#define BN0_WF_LPON_TOP_QCCR0_QUIET_EN_SHFT                    31
#define BN0_WF_LPON_TOP_QCCR0_QUIET_SOURCE_SEL_ADDR            BN0_WF_LPON_TOP_QCCR0_ADDR
#define BN0_WF_LPON_TOP_QCCR0_QUIET_SOURCE_SEL_MASK            0x60000000                // QUIET_SOURCE_SEL[30..29]
#define BN0_WF_LPON_TOP_QCCR0_QUIET_SOURCE_SEL_SHFT            29
#define BN0_WF_LPON_TOP_QCCR0_QUIET_TSF_TIME_ADDR              BN0_WF_LPON_TOP_QCCR0_ADDR
#define BN0_WF_LPON_TOP_QCCR0_QUIET_TSF_TIME_MASK              0x0000FFFF                // QUIET_TSF_TIME[15..0]
#define BN0_WF_LPON_TOP_QCCR0_QUIET_TSF_TIME_SHFT              0

/* =====================================================================================

  ---QCCR1 (0x820EB000 + 0x34c)---

    ACTIVE_PERIOD[7..0]          - (RW) Number of beacon intervals between the start of regularly scheduled quiet intervals
                                     MT7615 WIFI will use ACTIVE_PERIOD*TTPCR.BeaconPeriod as the actual active time for the quiet process. If the Active_Period is not 0, MT7615 WIFI will not assert the "Quite_Done" interrupt.
    RESERVED8[15..8]             - (RO) Reserved bits
    DURATION[31..16]             - (RW) Duration of each quiet interval
                                     Unit: TU

 =====================================================================================*/
#define BN0_WF_LPON_TOP_QCCR1_DURATION_ADDR                    BN0_WF_LPON_TOP_QCCR1_ADDR
#define BN0_WF_LPON_TOP_QCCR1_DURATION_MASK                    0xFFFF0000                // DURATION[31..16]
#define BN0_WF_LPON_TOP_QCCR1_DURATION_SHFT                    16
#define BN0_WF_LPON_TOP_QCCR1_ACTIVE_PERIOD_ADDR               BN0_WF_LPON_TOP_QCCR1_ADDR
#define BN0_WF_LPON_TOP_QCCR1_ACTIVE_PERIOD_MASK               0x000000FF                // ACTIVE_PERIOD[7..0]
#define BN0_WF_LPON_TOP_QCCR1_ACTIVE_PERIOD_SHFT               0

#ifdef __cplusplus
}
#endif

#endif // __BN0_WF_LPON_TOP_REGS_H__
